Datasheet

AFE0064
SLAS672 –SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com
As shown in Figure 9, the TFT injects a charge during turn on and an opposite polarity charge during turn off.
(For this example the injected charge during TFT turn on is positive.) This drives the integrator output –ve.
Depending on the magnitude of the injected charge, the integrator may saturate or may be within linear range.
The device starts integration from this –ve output voltage. At the end of integration the device sees an opposite
polarity charge injection roughly of the same magnitude. This opposite polarity charge may or may not nullify the
initial injected charge depending on whether the integrator was still within linear range or there was charge
leakage due to integrator output saturation. The voltage at pins 56, 57 can be adjusted so that the compensation
charge equals the TFT injected charge with opposite polarity. This nullifies the TFT injected charge both during
turn on and turn off, to always keep the integrator in the linear region. So for the positive charge injection during
TFT turn on, inject a –ve compensation charge. For this, the voltage at pins 56,57 needs to be set below the
voltage at 'EXT_C'. The device injects the charge on the falling edge of the DF_SM signal. The compensation
charge formulas are:
Compensation charge for TFT turn on = (V at pins 56,57 – V_'EXT_C') × 0.857 pC
Compensation charge for TFT turn off = –(V at pins 56,57 – V_'EXT_C') × 0.857 pC
Select voltage at pins 56,57 higher than the voltage at 'EXT_C' for compensating –ve charge during TFT turn on.
The device always injects an equal and opposite compensation charge at the rising edge of the DF_SM signal.
Allowing Limited Hole Counting (+ve charge) for Applications with Electron Counting (–ve charge) and
Vice a Versa:
The charge compensation scheme can be used to offset the integrator output at the start of integration so as to
allow a linear charge range in both directions. As discussed previously (refer to Figure 9), it is possible to inject a
fixed +ve or –ve charge at the start of integration. The device can integrate up or down starting from this offset
level. Note the integrator output is linear within the bounds of REFM and REFP. One can calculate the offset
charge at integration start as Qcomp = (V at pins 56,57 – V_'EXT_C') × 0.857 pC.
The resulting integrator o/p offset voltage in the case of integration up or down is given by the following formula:
In the case of integration up:
Vint_off = REFM – (Qcomp × Int FB cap) — Refer to Table 1 for the Int FB cap for the selected range.
Qcomp is negative for integration up, so that the integration output has a positive offset allowing headroom
for hole counting.
In the case of integration down:
Vint_off = REFP – (Qcomp × Int FB cap) — Refer to Table 1 for the Int FB cap for the selected range.
Qcomp is positive for integration up, so that the integration output has a negative offset allowing headroom
for electron counting.
As shown in Figure 10, DF_SM rising edge is pushed after SHS rising edge. This avoids opposite charge
injection which can corrupt integrator output.
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