Datasheet
TFTON
TFTOFF
SignalsampleBW
limitedbyfilter
LPFON
Signal Sample
SHR
SHS
INTG
Integrator
o/p
Reset Sample
AFE0064
SLAS672 –SEPTEMBER 2009 ........................................................................................................................................................................................
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In this period, the reset sample capacitor is tracking the integrator output voltage. On the 64th CLK falling edge,
the filter bypass switch is opened. This kicks in the low pass filter. The filter has a fixed time constant of 1 µSec
(160 kHz BW). The device samples and holds ( SHR switch opens) the integrator reset output at rising edge of
SHR. The low pass filter cuts off high frequency noise during sampling.
Figure 4. Timing Diagram Showing Details of Integration Phase
Here after the integration phase starts. The device integrates pixel charge during on time of the external TFT
switch. The device integrates pixel charge starting from the reset level (as described previously).
In integration up mode, the integrator output moves up from REFM (reset level). As shown in the Specifications
table there are 8 different ranges for the integrator. For any range, the device can linearly integrate input charge
until the integrator output reaches REFP.
In integration down mode, the integrator output moves down from REFP (reset level). For any analog input range
, the device can linearly integrate input charge until the integrator output reaches REFM.
It is clear that the linear output range for the integrator is ‘REFP-REFM’ volts. One can calculate the integrator
feedback capacitor with formula; Q = CV. Here Q is the specified charge for range ‘0 to 7’ and V is the linear
output range of the integrator (REFP-REFM). Refer to Table 1 for more details.
It is recommended to assert (pull high) the INTG signal along with TFT switch turn on. Note that the TFT switch
is external to the device, and the device still integrates without the INTG signal. INTG can be held high for 0.5
µSec after TFT switch turn off. This makes sure the SHS low pass filter is bypassed all through integration and
for 0.5 µSec after integration. This extra 0.5 µSec ensures charge injection during TFT switch turn off is settled
and the SHS sampling capacitor is tracking the integrator output. As shown in Figure 4, the device turns on the
LPF on the falling edge of INTG. Like SHR sampling, this filter has a 1 µSec time constant (160kHz BW), and it
cuts off high frequency noise during sampling. Timing ‘t6’ in the Timing Requirements table specifies that the
settling of voltage on the SHS capacitor is close to the 16 bit level while filter BW is low.
On the rising edge of SHS, the device samples and holds integrator output voltage on the correlated double
sampler (CDS). The CDS output voltage is proportional to the difference of the ‘SHS’ and ‘SHR’ samples. This
scheme removes offset and noise coming from integrator reset. The integration phase ends with the SHS falling
edge and data corresponding to all 64 channels is ready to read during the next ‘scan’.
Data Read:
Device output is differential even though the integrator output (internal to device) is single ended. Here is the
relation between integrator output and AFE0064 output ( OUTP and OUTM):
Case 1: ( Integrator up mode, INTUPz = 0)
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