Datasheet

ADS930
11
SBAS059A
are recommended to meet the rated performance specifica-
tions. However, the ADS930 performance is tolerant to duty
cycle variations of as much as ±10%, which should not
affect the performance. For applications operating with
input frequencies up to Nyquist (f
CLK
/2) or undersampling
applications, special considerations must be made to provide
a clock with very low jitter. Clock jitter leads to aperture
jitter (t
A
) which can be the ultimate limitation in achieving
good SNR performance. The following equation shows the
relationship between aperture jitter, input frequency and the
signal-to-noise ratio:
SNR = 20log10 [1/(2 π f
IN
t
A
)] (4)
LV
DD
, the digital output levels will vary respectively. It is
recommended to limit the fan-out to one in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
to provide the added benefit of isolating the ADC from any
digital activities on the bus coupling back high frequency
noise which degrades the performance.
POWER-DOWN MODE
The ADS930’s low power consumption can be reduced even
further by initiating a power-down mode. For this, the Power
Down Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 70%. In
normal operation, the power-down mode is disabled by an
internal pull-down resistor (50kΩ).
During power-down, the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition, the output data from the following 5 clock cycles
is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS930 has several supply pins, one of which is
dedicated to supply only the output driver (LV
DD
). The
remaining supply pins are not divided into analog and digital
supply pins since they are internally connected on the chip.
For this reason, it is recommended that the converter be
treated as an analog component and to power it from the
analog supply only. Digital supply lines often carry high
levels of noise which can couple back into the converter and
limit performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 8 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1µF ceramic chip capacitors
are adequate to keep the impedance low over a wide fre-
quency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close as possible to the supply pins.
DIGITAL OUTPUTS
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS930 can be set to a high impedance state by driving
the OE (pin 16) with a logic “HI”. Normal operation is
achieved with pin 16 “LO” or Floating due to internal pull-
down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
The digital outputs of the ADS930 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: V
OL
= 0.4V, V
OH
= 2.4V, which allows
the ADS930 to directly interface to 3V-logic. The digital
output driver of the ADS930 uses a dedicated digital supply
pin (pin 2, LV
DD
) see Figure 7. By adjusting the voltage on
TABLE I. Coding Table for the ADS930.
+FS (IN = +2V) 11111111
+FS –1LSB 11111111
+FS –2LSB 11111110
+3/4 Full Scale 11100000
+1/2 Full Scale 11000000
+1/4 Full Scale 10100000
+1LSB 10000001
Bipolar Zero (IN +1.5V) 10000000
–1LSB 01111111
–1/4 Full Scale 01100000
–1/2 Full Scale 01000000
–3/4 Full Scale 00100000
–FS +1LSB 00000001
–FS (IN = +1V) 00000000
STRAIGHT OFFSET BINARY
(SOB)
SINGLE-ENDED INPUT PIN 12
(IN = 1.5V DC) FLOATING or LO
+V
S
+LV
DD
ADS930
Digital
Output
Stage
FIGURE 7. Independent Supply Connection for Output
Stage.
V
S
1
13
14
GND
ADS930
0.1µF
V
S
18
19
20
GND
0.1µF
V
S
28
0.1µF
FIGURE 8. Recommended Bypassing for Analog Supply
Pins.