Datasheet

ADS900
8
SBAS058A
FIGURE 1. Input Track-And-Hold Configuration with
Timing Signals.
FIGURE 2. Pipeline A/D Architecture.
THEORY OF OPERATION
The ADS900 is a high speed sampling ADC that utilizes a
pipeline architecture. The fully differential topology and
digital error correction guarantee 10-bit resolution. The
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock which has a non-overlapping
two phase signal, φ1 and φ2. At the sampling time the input
signal is sampled on the bottom plates of the input capaci-
tors. In the next clock phase, φ2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time the
charge redistributes between C
I
and C
H
, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. In the
normal mode of operation, the complementary input is tied
to the common-mode voltage. In this case, the track-and-
hold circuit converts a single-ended input signal into a fully
differential signal for the quantizer. Consequently, the input
signal gets amplified by a gain or two, which improves the
signal-to-noise performance. Other parameters such as small-
signal and full-power bandwidth, and wideband noise are
also defined in this stage.
φ 1
φ 1
φ 2 φ 1
φ 1 φ 1
φ 1
φ 1
φ 2
φ 1 φ 2 φ 1
φ 2
IN
IN
(Opt.)
OUT
OUT
Op Amp
Bias
V
CM
Op Amp
Bias
V
CM
C
H
C
I
C
I
C
H
Input Clock (50%)
Internal Non-overlapping Clock
Σ
+
–
B1 (MSB)
B2
B3
B4
B5
B6
B7
B8
B9
B10 (LSB)
2-Bit
DAC
2-Bit
Flash
Input
T/H
Digital Delay
x2
x2
2-Bit
DAC
2-Bit
Flash
Digital Delay
2-Bit
Flash
Digital Delay
2-Bit
DAC
2-Bit
Flash
Digital Delay
x2
Digital Error Correction
IN
IN
STAGE 1
STAGE 2
STAGE 8
STAGE 9
Σ
+
–
Σ
+
–
(Opt.)