Datasheet

ADS900
4
SBAS058A
5 Clock Cycles
Data Invalid
t
D
t
L
t
H
t
CONV
N–5N–4N–3N–2N–1 N N+1 N+2
Data Out
Clock
Analog In
N
t
2
N+1
N+2
N+3
N+4
N+5
N+6
N+7
t
1
PIN CONFIGURATION
PIN DESIGNATOR DESCRIPTION
1+V
S
Analog Supply
2LV
DD
Output Logic Driver Supply Voltage
3 Bit 10 Data Bit 10 (D0) (LSB)
4 Bit 9 Data Bit 9 (D1)
5 Bit 8 Data Bit 8 (D2)
6 Bit 7 Data Bit 7 (D3)
7 Bit 6 Data Bit 6 (D4)
8 Bit 5 Data Bit 5 (D5)
9 Bit 4 Data Bit 4 (D6)
10 Bit 3 Data Bit 3 (D7)
11 Bit 2 Data Bit 2 (D8)
12 Bit 1 Data Bit 1 (D9) (MSB)
13 GND Analog Ground
14 GND Analog Ground
15 CLK Convert Clock Input
16 OE Output Enable, Active Low
17 Pwrdn Power Down Pin
18 +V
S
Analog Supply
19 GND Analog Ground
20 GND Analog Ground
21 LpBy Positive Ladder Bypass
22 NC No Connection
23 1V
REF
1V Reference Output
24 IN Complementary Input
25 LnBy Negative Ladder Bypass
26 CM Common-Mode Voltage Output
27 IN Analog Input
28 +V
S
Analog Supply
PIN DESCRIPTIONS
Top View SSOP
TIMING DIAGRAM
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
CONV
Convert Clock Period 50 100µsns
t
L
Clock Pulse Low 24 25 ns
t
H
Clock Pulse High 24 25 ns
t
D
Aperture Delay 2 ns
t
1
Data Hold Time, C
L
= 0pF 3.9 ns
t
2
New Data Delay Time, C
L
= 15pF max 12 ns
+V
S
LV
DD
LSB Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
MSB Bit 1
GND
GND
+V
S
IN
CM
LnBy
IN
1V
REF
NC
LpBy
GND
GND
+V
S
Pwrdn
OE
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS900