Datasheet

ADS900
11
SBAS058A
proper op amp should include its output swing, input com-
mon-mode range, and bias current. It should be noted that
any DC voltage difference between the inputs, IN and IN,
will show up as an offset at the output. At the same time an
offset adjustment can be accomplished.
INTERNAL REFERENCE
The ADS900 features an internal pipeline reference that
provides fixed reference voltages for the internal stages. As
shown in Figure 7 a buffer for each the top and bottom
reference is connected to the resistor ladder, which has a
nominal resistance of 4kΩ (±15%). The two outputs of the
buffers are brought out at pin 21 (LpBy) and pin 25 (LnBy),
primarily to connect external bypass capacitors, typically
0.1µF, which will improve the performance. The buffers can
drive limited external loads, for example for level shifting of
the converter’s interface circuit, however, the current draw
should be limited to approximately 1mA.
Derived from the top reference of +1.75V is an additional
voltage of +1.0V. Note that this voltage, available on pin 23,
is not buffered and care should be taken when external loads
are applied. In normal operation, this pin is left unconnected
and no bypassing components are required.
CLOCK INPUT REQUIREMENTS
The clock input of the ADS900 is designed to accommodate
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support maximum sampling rates (20Msps) high speed or
advanced CMOS logic should be used (HC/HCT, AC/ACT).
When digitizing at high sampling rates, a 50% duty cycle
along with fast rise and fall times (2ns or less) are recom-
mended to meet the rated performance specifications. How-
ever, the ADS900 performance is tolerant to duty cycle
variations of as much as ±10% without degradation. For
applications operating with input frequencies up to Nyquist
or undersampling applications, special considerations must
be made to provide a clock with very low jitter. Clock jitter
leads to aperture jitter (t
A
) which can be the ultimate limita-
tion in achieving good SNR performance. The following
equation shows the relationship between aperture jitter,
input frequency and the signal-to-noise ratio:
SNR = 20log
10
[1/(2 π f
IN
t
A
)] (4)
For example, in the case of a 10MHz full-scale input signal
and an aperture jitter of t
A
= 20ps the SNR is clock jitter
limited to 58dB.
DIGITAL OUTPUTS
The digital outputs of the ADS900 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: V
OL
= 0.4V, V
OH
= 2.4V, which allows
the ADS900 to directly interface to 3V-logic. The digital
outputs of the ADS900 uses a dedicated digital supply pin
(pin 2, LV
DD
) see Figure 8. By adjusting the voltage on
LV
DD
, the digital output levels will vary respectively. It is
recommended to limit the fan-out to one to keep the capaci-
tive loading on the data lines below the specified 15pF. If
necessary, external buffers or latches may be used which
provide the added benefit of isolating the ADC from any
digital activities on the bus coupling back high frequency
noise and degrading the performance.
FIGURE 7. Internal Reference Structure and Recommended Reference Bypassing.
ADS900
2.8kΩ
2kΩ
2kΩ
+1.75V
+1.25V
2.1kΩ
0.1µF
REFT
REFB
LpBy
21
23
26
25
+1V
REF
0.1µF
LnBy
0.1µF
CM