Datasheet
SCLK
AVDD, HVDD,
HVSS Current
CS
I
DYNAMIC
I
STATIC
16f 16f
t
DYNAMIC =
1/f
SAMPLE (Max)
t
FRAME
=1/f
SAMPLE (Actual)
t
STATIC
ADS8634
ADS8638
SBAS541A –MAY 2011– REVISED AUGUST 2011
www.ti.com
POWER MANAGEMENT AT LOWER SPEEDS
There are multiple data acquisition applications that require sampling speeds much lower than 1MSPS. The
ADS8634/8 offer power saving while running at lower speeds. As shown in Figure 92, the ADS8634/8 consume
dynamic power from a CS rising edge until the 16th SCLK falling edge. While using the ADS8634/8 at lower
sampling speeds, it is recommended to use SCLK at the maximum specified frequency. This setting allows the
maximum static period t
STATIC
at any given sampling speed. The ADS8634/8 consume considerably lower static
current (current during t
STATIC
) from all three power supplies (AVDD, HVDD, and HVSS). This consumption helps
lower the average currents from each of the supplies, resulting in a lower average power consumption while
using the device at lower sampling speeds.
Figure 92. Supply Current Profile at Speeds Below 1MSPS
Table 15 shows t
FRAME
, t
DYNAMIC
, and t
STATIC
at a 0.1MSPS sampling speed.
Table 15. Typical Static/Dynamic Time Distribution at Lower Speeds (0.1MSPS)
f
SAMPLE
(MSPS) t
FRAME
(µs) t
DYNAMIC
(µs) t
STATIC
(µs)
0.1 10 1 9
The average device power consumption can be calculated with Equation 8 and Equation 9:
Average Current, I
AVERAGE
= (I
DYNAMIC
× t
DYNAMIC
+ I
STATIC
× t
STATIC
)/(t
DYNAMIC
+ t
STATIC
) (8)
Average Power = Supply Voltage × I
AVERAGE
(9)
Table 16 shows the average power calculations at 0.1MSPS.
Table 16. Average Power Calculations at 0.1MSPS
PARAMETER AVDD HVDD HVSS
Typical supply voltage (V) 3.3 10 10
I
DYNAMIC
(mA) 2.50 0.27 0.35
t
DYNAMIC
(µs) 1.0 1.0 1.0
I
STATIC
(mA) 1.45 0.005 0.005
t
STATIC
(µs) 9.0 9.0 9.0
Average current, I
AVERAGE
(mA) 1.555 0.032 0.040
Average power (mW) 5.132 0.315 0.395
Total average power (mW) = P
AVDD
+ P
HVDD
+ P
HVSS
5.842
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