Datasheet

+
50Ω
20Ω
1200pF
OPA140
ADS8634/8
AINx
AINGND
AVDD
AGND
+VA
HVDD
V
OPA+
HVSS
V
OPA
Analog
Signal
V
RANGE
V
OPA+
V
OPA
SamplingTime
SettlingResolution ln(2)´
FilterTimeConstant(t )=
AU
FilterTimeConstant(t )=R C´
AU
1
2 t´ p ´
AU
FilterBandwidth=
ADS8634
ADS8638
www.ti.com SBAS541A –MAY 2011– REVISED AUGUST 2011
APPLICATION INFORMATION
DRIVING ANALOG SIGNAL INPUT
The ADS8634/8 employ a sample-and-hold stage at the input. An 8pF sampling capacitor is connected during
sampling. This configuration results in a glitch at the input terminals of the device at the start of the sample. The
external circuit must be designed in such a way that the input can settle to the required accuracy during the
chosen sampling time. Figure 91 shows a reccomended driving circuit for the analog inputs.
Figure 91. Reccomended Driving Circuit
The 8pF capacitor across the AINx and AINGND terminals decouples the driving op amp from the sampling
glitch. The low-pass filter at the input limits noise bandwidth of the driving op amp. Select the filter bandwidth so
that the full-scale step at the input can settle to the required accuracy during the sampling time. Equation 5,
Equation 6, and Equation 7 are useful for filter component selection.
Where:
Settling resolution is the accuracy in LSB to which the input must settle. A typical settling resolution for
the 12-bit device is 13 or 14. (5)
(6)
(7)
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth to below the filter bandwidth.
In many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional
low-pass filter may be used at the input of the driving op amp. This signal and filter bandwidth can be selected in
accordance with the input signal bandwidth.
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