Datasheet

A6 A5 A0 D7 D6 D1 D0
CS
SCLK
DIN
DOUT
W
A6 A5 A0 D7 D6 D1 D0
D7 D6 D1 D0
CS
SCLK
DIN
DOUT
R
ADS8634
ADS8638
www.ti.com SBAS541A –MAY 2011– REVISED AUGUST 2011
SPI REGISTER WRITE CYCLE
Figure 89 shows a timing diagram of the SPI write cycle. The device executes the command on the first CS
falling edge after a command write cycle. The only exception to this command execution timing is the
power-down command. The power-down command (through a register write) is executed on the 16th falling edge
of SCLK. This falling edge occurs immediately after the last command bit is written to the device.
Figure 89. Write Cycle
SPI REGISTER READ CYCLE
Figure 90 shows a timing diagram of the SPI read cycle.
Figure 90. Read Cycle
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