Datasheet
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REFIO
REFBN
AGND
REFN
REFCP
AGND
REFCN
CH_C0
CH_C1
AVDD
CH_B0
REFBP
CH_B1
AGND
AVDD
AVDD
R
F
R
F
10 Fm
C
F
ToHVDD
TtoHVSS
LEGEND
TopLayer;CopperPourandTraces
LowerLayer;AGNDArea
LowerLayer;DGNDArea
Via
C
F
10 Fm
10 Fm 10 Fm
10 Fm
10 Fm
R
F
C
F
R
F
R
F
R
F
C
F
C
F
C
F
0.1 Fm
0.47 Fm
0.1 Fm
R
F
C
F
R
F
C
F
REFAN
CH_A1
HVDD
AVDD
AGND
REFAP
CH_A0
41
40
39
38
37
36
35
34
33
17
18 19 20 23 29
26
27
DVDD
30
31
32
28
21 22
DGND
HVSS
CH_D1
REFDN
AVDD
CH_D0
8
REFDP
AGND
9
10
11
12
AGND
16
AVDD
13
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011– REVISED OCTOBER 2011
(1) All AVDD/DVDD decoupling capacitors are placed on the bottom layer underneath the device power-supply pins and are connected by
vias. All 100nF ceramic capacitors are placed as close as possible to the device while the 10µF capacitors are also close but without
compromising the placement of the smaller capacitors.
Figure 44. Layout Recommendation
Copyright © 2011, Texas Instruments Incorporated 41
Product Folder Link(s): ADS8528 ADS8548 ADS8568