Datasheet

CONVST_A/B/D
BUSY
(C27=C26=0)
DB[15:0]
RD
CH
A0
CH
A1
CONVST_B
DB[15:0]
CONVST_A/D
RD
CH
B0
CH
B1
CH
D0
CH
D1
CH
A0
CH
A1
OldData
SameData(Reread)
OldData OldData(Reread)
CH
A0
CH
A1
CH
B0
CH
B1
CH
D0
CH
D1
CH
A0
CH
A1
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011– REVISED OCTOBER 2011 www.ti.com
While the standby mode impacts the entire device, each device channel pair (except channel pair A, which as
the master channel pair, is always active) can also be individually switched off by setting the Configuration
Register bits C22, C20, and C18 (PD_x). If a certain channel pair is powered-down in this manner, the output
register is disabled as shown in Figure 41. When reactivated, the relevant channel pair requires 10ms to fully
settle before starting a new conversion.
(1) Channel pair C disabled (PD_C = 1), CS = 0.
NOTE: Boxed areas indicate the minimum required frame to acquire all new conversion results. The read access might be interrupted,
thereafter.
Figure 41. Example of Data Output Order with Channel Pair C Powered Down
(1)
36 Copyright © 2011, Texas Instruments Incorporated
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