Datasheet

ADS8528
ADS8548
ADS8568
www.ti.com
SBAS543A AUGUST 2011 REVISED OCTOBER 2011
Output Data Format
The data output format of the ADS8528/48/68 is binary twos complement, as shown in Table 7. For the
ADS8528/48 (which deliver 12-bit or 14-bit conversion results, respectively), the leading bits of either the 16-bit
frame (serial interface) or the output pins (DB[15:12] for the ADS8528 or DB[15:14] for the ADS8548 in parallel
mode) deliver a sign extension.
Table 7. Output Data Format
BINARY CODE HEXADECIMAL CODE
DESCRIPTION INPUT VOLTAGE VALUE ADS8528 ADSS8548 ADS8568
0000 0111 1111 1111 0001 1111 1111 1111 0111 1111 1111 1111
Positive full-scale +4VREF or +2VREF
07FFh 1FFFh 7FFFh
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Midscale +0.5LSB VREF/(2 × resolution)
0000h 0000h 0000h
1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
Midscale 0.5LSB VREF/(2 × resolution)
FFFFh FFFFh FFFFh
1111 1000 0000 0000 1110 0000 0000 0000 1000 0000 0000 0000
Negative full-scale 4VREF or 2VREF
F800h E000h 8000h
Reset and Power-Down Modes
The device supports two reset mechanisms: a power-on reset (POR) and a pin-controlled reset (RESET) that
can be issued using pin 10. Both, the POR and RESET act as a master reset that causes any ongoing
conversion to be interrupted, the Configuration Register content to be set to the default value, and all channels to
be switched into the sample mode.
When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.2V. In normal
operation, glitches on the AVDD supply below this threshold trigger a device reset.
The entire device, except for the digital interface, can be powered down by pulling the STBY pin low (pin 9). As
the digital interface section remains active, data can be retrieved while in stand-by mode. To power the part on
again, the STBY pin must be brought high. The device is ready to start a new conversion after the 10ms required
to activate and settle the internal circuitry. This user-controlled approach can be used in applications that require
lower data throughput rates at lowest power dissipation. The content of CONFIG is not changed during stand-by
mode and it is not required to perform a reset after returning to normal operation.
Copyright © 2011, Texas Instruments Incorporated 35
Product Folder Link(s): ADS8528 ADS8548 ADS8568