Datasheet
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011– REVISED OCTOBER 2011
Configuration (CONFIG) Register
The Configuration Register settings can only be changed in software mode and are not affected when switching
to hardware mode thereafter. The register values are independent from input pin settings. Changes are active
with the second rising edge of WR in parallel interface mode or with the 32nd SCLK falling edge of the access in
which the register content has been updated in serial mode. The CONFIG content is defined in Table 6.
Table 6. CONFIG: Configuration Register (Default: 000003FFh)
31 30 29 28 27 26 25 24
WRITE_EN READ_EN CLKSEL CLKOUT BUSY/INT BUSY POL STBY RANGE_A
23 22 21 20 19 18 17 16
RANGE_B PD_B RANGE_C PD_C RANGE_D PD_D Don't care Don't care
15 14 13 12 11 10 9 8
REFEN REFBUF VREF Don't care Don't care Don't care D9 D8
7 6 5 4 3 2 1 0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 31 WRITE_EN: Register update enable
This bit is not active in hardware mode.
0 = Register content update disabled (default)
1 = Register content update enabled
Bit 30 READ_EN: Register read-out access enable
This bit is not active in hardware mode.
0 = Normal operation (conversion results available on SDO_A)
1 = Configuration Register contents output on SDO_A with next two accesses
(READ_EN automatically resets to '0' thereafter)
Bit 29 CLKSEL: Conversion clock selector
This bit is active in hardware mode.
0 = Normal operation with internal conversion clock; mandatory in hardware mode (default)
1 = External conversion clock applied through pin 34 (XCLK) is used (conversion takes 19
clock cycles)
Bit 28 CLKOUT: Internal conversion clock output enable
This bit is not active in hardware mode.
0 = Normal operation (default)
1 = Internal conversion clock is available at pin 34
Bit 27 BUSY/INT: Busy/interrupt selector
This bit is active in hardware mode.
0 = BUSY/INT pin in BUSY mode (default)
1 = BUSY/INT pin in interrupt mode (INT); can only be used if all eight channels are
sampled simultaneously (all CONVST_x tied together)
Bit 26 BUSY POL: BUSY/INT polarity selector
This bit is active in hardware mode.
0 = BUSY/INT active high (default)
1 = BUSY/INT active low
Bit 25 STBY: Power-down enable
This bit is not active in hardware mode.
0 = Normal operation (default)
1 = Entire device is powered down (including the internal clock and reference)
Copyright © 2011, Texas Instruments Incorporated 31
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