Datasheet
f =
3dB
ln(2)
2 tp
CONV
ADS8528
ADS8548
ADS8568
www.ti.com
SBAS543A –AUGUST 2011– REVISED OCTOBER 2011
The voltage at the REFIO pin is buffered with four internal amplifiers, one for each ADC pair. The output of each
buffer must be decoupled with a 10µF capacitor between the pin pairs 3 and 6, 43 and 46, 50 and 53, and 60
and 63. The 10µF capacitors are available as ceramic 0805-SMD components and in X5R quality.
The internal reference buffers can be powered down to decrease the power dissipation of the device. In this
case, external reference drivers can be connected to the REFAP, REFBP, REFCP, and REFDP pins. With 10µF
decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4:
(4)
With the minimum t
CONV
of 1.33µs, the external reference buffers require a minimum bandwidth of 83kHz.
DIGITAL
This section describes the digital control and the timing of the device in detail.
Device Configuration
Depending on the desired mode of operation, the ADS8528/48/68 can be configured using the external pins
and/or the Configuration Register (CONFIG), as shown in Table 5.
Table 5. ADS8528/48/68 Configuration Settings
INTERFACE MODE HARDWARE MODE (HW/SW = 0) SOFTWARE MODE (HW/SW = 1)
Configuration using pins and (optionally) Configuration Configuration using Configuration Register bits C[31:0]
Parallel (PAR/SER = 0) Register bits C30, C29, C[27:26], C22, C20, C18, C14, only; status of pins 9, 11, 20, and 34 are disregarded
C13, and C[9:0] (if C29 = C28 = 0)
Configuration using pins and (optionally) Configuration Configuration using Configuration Register bits C[31:0]
Serial (PAR/SER = 1) Register bits C30, C29, C[27:26], C22, C20, C18, C13, only; status of pins 9, 11, 20, and 34 are disregarded
and C[9:0] (if C29 = C28 = 0)
Hardware Mode
With the HW/SW input (pin 41) set low, the device functions are controlled via the pins and, optionally,
Configuration Register bits C30, C29, C[27:26], C22, C20, C18, C14 (in parallel interface mode only), C13, and
C[9:0].
It is possible to generally use the part in hardware mode but to switch it into software mode to initialize or adjust
the Configuration Register settings (for example, the internal reference DAC) and back to hardware mode
thereafter.
Software Mode
When the HW/SW input is set high, the device operates in software mode with functionality set only by the
Configuration Register bits (corresponding pin settings are ignored).
If parallel interface is used, an update of all Configuration Register settings is performed by issuing two 16-bit
write accesses on pins DB[15:0] (to avoid loosing data, the entire sequence must be finished before starting a
new conversion). CS should be held low during these two accesses. To enable the actual update of the register
settings, the first bit (C31) must be set to '1' during the access.
Copyright © 2011, Texas Instruments Incorporated 29
Product Folder Link(s): ADS8528 ADS8548 ADS8568