Datasheet
CONVST_A,C
BUSY
(C27=C26=0)
CS
DB[15:0]
RD
CH
A0
CH
A1
CONVST_B
DB[15:0]
CONVST_A,C,D
RD
CONVST_B,D
CH
B0
CH
B1
CH
C0
CH
C1
CH
D0
CH
D1
OldData OldData
OldData OldData
CH
A0
CH
A1
CH
B0
CH
B1
CH
C0
CH
C1
CH
D0
CH
D1
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011– REVISED OCTOBER 2011
CONVST_x
The analog inputs of each channel pair (CH_x0/1) are held with the rising edge of the corresponding CONVST_x
signal. The conversion automatically starts with the next rising edge of the conversion clock. CONVST_A is a
master conversion start that resets the internal state machine and causes the data output to start with the result
of channel A0. In cases where channel pairs of the device are used at different data rates, CONVST_A should
always be the one used at the highest frequency.
A conversion start must not be issued during an ongoing conversion on the corresponding channel pair. It is
allowed to initiate conversions on the other input pairs, however.
If a parallel interface is used, the content of the output port depends on which CONVST_x signals have been
issued. Figure 36 shows examples of different scenarios with all channel pairs active.
Figure 36. Data Output versus CONVST_x (All Channels Active)
Copyright © 2011, Texas Instruments Incorporated 27
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