Datasheet

ADS8528
ADS8548
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www.ti.com SBAS543A –AUGUST 2011– REVISED OCTOBER 2011
PIN DESCRIPTIONS (continued)
DESCRIPTION
PIN # NAME TYPE
(1)
PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)
Auto-sleep enable input.
When low, the device operates in normal mode.
36 ASLEEP DI When high, the device works in auto-sleep mode where the hold mode and the actual conversion is activated 6
conversion clock (t
CCLK
) cycles after issuing a conversion start using a CONVST_x. This mode is recommended to
save power if the device runs at a lower data rate; see the Reset and Power-Down Modes section for more details.
Conversion start of channel pair A.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0].
37 CONVST_A DI
This signal resets the internal channel state machine that causes the data output to start with conversion results of
channel A0 with the next read access.
Conversion start of channel pair B.
38 CONVST_B DI
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0].
Conversion start of channel pair C.
39 CONVST_C DI
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0].
Conversion start of channel pair D.
40 CONVST_D DI
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_D[1:0].
Mode selection input.
When low, the hardware mode is selected and the device functions according to the settings of the external pins.
41 HW/SW DI
When high, the software mode is selected in which the device is configured by writing to the Configuration Register
(CONFIG).
Analog input of channel A0; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in
42 CH_A0 AI
software mode. In cases where channel pairs of the device are used at different data rates, channel pair A should
always run at the highest data rate.
Decoupling capacitor input for reference of channel pair A.
43 REFAP AI
Connect to the decoupling capacitor according to the Power Supply section.
Decoupling capacitor input for reference of channel pair A.
46 REFAN AI
Connect to the decoupling capacitor and AGND according to the Power Supply section.
Analog input of channel A1; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in
47 CH_A1 AI
software mode. In cases where channel pairs of the device are used at different data rates, channel pair A should
always run at the highest data rate.
Positive supply voltage for the analog inputs.
48 HVDD P
Decouple according to the Power Supply section.
Analog input of channel B0.
49 CH_B0 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in
software mode.
Decoupling capacitor input for reference of channel pair B.
50 REFBP AI
Connect to the decoupling capacitor according to the Power Supply section.
Decoupling capacitor input for reference of channel pair B.
53 REFBN AI
Connect to the decoupling capacitor and AGND according to the Power Supply section.
Analog input of channel B1.
54 CH_B1 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in
software mode.
Negative reference input/output pin.
55 REFN AI
Connect to a decoupling capacitor and AGND according to the Power Supply section.
Reference voltage input/output.
The internal reference is enabled by the REFEN/WR pin in hardware mode or by CONFIG bit C15 (REFEN) in
56 REFIO AIO
software mode. The output value is controlled by the internal DAC (CONFIG bits C[9:0]).
Connect to a decoupling capacitor according to the Power Supply section.
Analog input of channel C1.
59 CH_C1 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in
software mode.
Decoupling capacitor input for reference of channel pair C.
60 REFCN AI
Connect to the decoupling capacitor and AGND according to the Power Supply section.
Decoupling capacitor input for reference of channel pair C.
63 REFCP AI
Connect to the decoupling capacitor according to the Power Supply section.
Analog input of channel C0.
64 CH_C0 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in
software mode.
Copyright © 2011, Texas Instruments Incorporated 17
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