Datasheet
CS
DB[15:0]
WR
t
CSWR
t
HDI
t
WRL
t
SUDI
C
[31:16]
t
WRCS
t
WRH
C
[15:0]
R =200
SER
W R =130
SW
W
R =200W
SER
R =130
SW
W
C =5pF
PAR
C =20pF
S
C =20pF
S
CH_XX
AGND
Inputrange: 2VREF±
V
DC
R =200
SER
W R =130
SW
W
R =200W
SER
R =130
SW
W
C =5pF
PAR
C =10pF
S
C =10pF
S
CH_XX
AGND
Inputrange: 4VREF±
V
DC
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011– REVISED OCTOBER 2011
www.ti.com
Figure 3. Parallel Write Access Timing Diagram
Table 3. Parallel Interface Timing Requirements (Write Access)
(1)(2)
ADS8528, ADS8548, ADS8568
PARAMETER MIN TYP MAX UNIT
t
CSWR
CS low to WR low time 0 ns
t
WRL
WR low pulse width 15 ns
t
WRH
Minimum time between two write accesses 10 ns
t
WRCS
WR high to CS high time 0 ns
t
SUDI
Output data to WR rising edge setup time 5 ns
t
HDI
Data output to WR rising edge hold time 5 ns
(1) Over recommended ambient temperature range T
A
, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted.
(2) All input signals are specified with t
R
= t
F
= 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
EQUIVALENT CIRCUITS
Figure 4. Equivalent Input Circuits
12 Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8528 ADS8548 ADS8568