ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com 12-, 14-, 16-Bit, Eight-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS Check for Samples: ADS8528, ADS8548, ADS8568 FEATURES DESCRIPTION • The ADS8528/48/68 contain eight low-power, 12-, 14-, or 16-bit, successive approximation register (SAR)-based analog-to-digital converters (ADCs) with true bipolar inputs.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8528 All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8548 All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8568 All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V. ADS8528, ADS8548, ADS8568 PARAMETER CONDITIONS MIN TYP MAX UNIT ADS8528, fDATA = maximum 3.4 4.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION TIMING CHARACTERISTICS XCLK (C29 = 1) tSCVX tCVL tXCLK CONVST_x tACQ tCONV tDCVB BUSY (C27 = C26 = 0) tFSCV tBUFS FS tSCLK 32 1 SCLK tHDO tPDDO tDMSB CH_x0 MSB SDO_x CH_x1 D3 CH_x1 D2 tDTRI CH_x1 D1 tSUDI SDI or DCIN_x Don’t Care D31 D3 CH_x1 LSB tHDI D2 D1 D0 Don’t Care Figure 1.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Table 1. Serial Interface Timing Requirements (1) (2) TEST CONDITION PARAMETER tSCVX tXCLK CONVST_x high to XCLK rising edge setup time External conversion clock period External conversion clock frequency CLKSEL = 1 CONVST_x low time tACQ Acquisition time MIN TYP ADS8528 66.67 ns ADS8548 72.46 ns ADS8568 85.11 ADS8528 1 ADS8548 ADS8568 ns 15.0 MHz 1 13.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com tCVL CONVST_x tCONV tACQ tDCVB BUSY (C27 = C26 = 0) tBUCS tCSCV CS tCSRD tRDCS tRDL tRDH RD tPDDO CH A0 DB[15:0] CH A1 CH B0 CH B1 tHDO CH C0 CH C1 tDTRI CH D0 CH D1 Figure 2. Parallel Read Access Timing Diagram Table 2.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com CS tCSWR tWRL tWRH tWRCS WR tSUDI tHDI C [31:16] DB[15:0] C [15:0] Figure 3. Parallel Write Access Timing Diagram Table 3.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PIN DESCRIPTIONS DESCRIPTION PIN # NAME TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) 1 HVSS P Negative supply voltage for the analog inputs. Decouple according to the Power Supply section. 2 CH_D1 AI Analog input of channel D1. The input voltage range is controlled by the RANGE pin in hardware mode or by the Configuration Register (CONFIG) bit C19 (RANGE_D) in software mode.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PIN DESCRIPTIONS (continued) DESCRIPTION PIN # NAME TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) DB11/REFBUFE N DIO/DI 21 DB10/SCLK DIO/DI Data bit 10 input/output 22 DB9/SDI DIO/DI Data bit 9 input/output 23 DB8/DCEN DIO/DI Data bit 8 input/output 24 DGND P Buffer I/O ground, connect to digital ground plane 25 DVDD P Buffer I/O supply, connect to digital supply.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PIN DESCRIPTIONS (continued) DESCRIPTION PIN # NAME TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) 36 ASLEEP DI Auto-sleep enable input. When low, the device operates in normal mode. When high, the device works in auto-sleep mode where the hold mode and the actual conversion is activated 6 conversion clock (tCCLK) cycles after issuing a conversion start using a CONVST_x.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. INL vs CODE (ADS8528) DNL vs CODE (ADS8528) 0.75 0.5 0.4 0.5 0.3 0.2 DNL (LSB) INL (LSB) 0.25 0 −0.25 0.1 0 −0.1 −0.2 −0.3 −0.5 −0.4 500 1000 1500 2000 Code 2500 3000 3500 −0.5 4000 0.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. PSRR vs SUPPLY NOISE FREQUENCY CONVERSION TIME vs TEMPERATURE Power-Supply Rejection Ratio (dB) −40 1.8 CSUPPLY = 100nF on AVDD CSUPPLY = 1µF on HVDD CSUPPLY = 1µF on HVSS 1.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (3.0V Mode) ADS8568 ANALOG SUPPLY CURRENT vs TEMPERATURE 3.015 50 fDATA = MAX fDATA = 250kSPS (Auto-Sleep) 46 3.01 42 IAVDD (mA) VREF (V) 3.005 3 2.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. IHVxx (mA) ADS8568 INPUT SUPPLY CURRENT vs DATA RATE 4.5 4.25 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com GENERAL DESCRIPTION The ADS8528/48/68 series includes eight 12-, 14-, and 16-bit analog-to-digital converters (ADCs), respectively, that operate based on the successive approximation register (SAR) architecture. This architecture is designed on the charge redistribution principle, which inherently includes a sample-and-hold function. The eight analog inputs are grouped into four channel pairs.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com A driving operational amplifier may not be required, if the impedance of the signal source (RSOURCE) fulfills the requirement of Equation 2: tACQ RSOURCE < - (RSER + RSW) CS ln(2)(n + 1) (2) where: n = 12, 14, or 16; n is the resolution of the ADC, CS = 10pF is the sample capacitor value in VIN = ±4VREF mode, RSER = 200Ω is the input resistor value, and RSW = 130Ω is the switch resistance value.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com CONVST_x The analog inputs of each channel pair (CH_x0/1) are held with the rising edge of the corresponding CONVST_x signal. The conversion automatically starts with the next rising edge of the conversion clock. CONVST_A is a master conversion start that resets the internal state machine and causes the data output to start with the result of channel A0.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com BUSY/INT The BUSY signal indicates if a conversion is in progress. It goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective output register. The readout of the data can be initiated immediately after the falling edge of BUSY.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com The voltage at the REFIO pin is buffered with four internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10µF capacitor between the pin pairs 3 and 6, 43 and 46, 50 and 53, and 60 and 63. The 10µF capacitors are available as ceramic 0805-SMD components and in X5R quality. The internal reference buffers can be powered down to decrease the power dissipation of the device.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com If the serial interface is used, the update of the register contents can be performed continuously (combined read/write access). Optionally, to reduce the data transfer on the SDI line and the electromagnetic interference (EMI) of the system, the SDI input can be pulled low when a register update is not required. Figure 38 illustrates the different Configuration Register update options.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Configuration (CONFIG) Register The Configuration Register settings can only be changed in software mode and are not affected when switching to hardware mode thereafter. The register values are independent from input pin settings. Changes are active with the second rising edge of WR in parallel interface mode or with the 32nd SCLK falling edge of the access in which the register content has been updated in serial mode.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 Bit 24 www.ti.com RANGE_A: Input voltage range selector for channel pair A This bit is not active in hardware mode. 0 = Input voltage range: 4VREF (default) 1 = Input voltage range: 2VREF Bit 23 RANGE_B: Input voltage range selector for channel pair B This bit is not active in hardware mode.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Parallel Interface To use the device with the parallel interface, the PAR/SER pin should be held low. The maximum achievable data throughput rate is 650kSPS for the ADS8528, 600kSPS for the ADS8548, and 510kSPS for the ADS8568 in this case. Access to the ADS8528/48/68 is controlled as illustrated in Figure 2 and Figure 3. Serial Interface The serial interface mode is selected by setting the PAR/SER pin high.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Daisy-Chain Mode The serial interface of the ADS8528/48/68 supports a daisy-chain feature that allows cascading of multiple devices to minimize the board space requirements and simplify routing of the data and control lines. In this case, pins DB3/DCIN_A, DB2/DCIN_B, DB1/DCIN_C, and DB0/DCIN_D are used as serial data inputs for channels A, B, C, and D, respectively.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Output Data Format The data output format of the ADS8528/48/68 is binary twos complement, as shown in Table 7. For the ADS8528/48 (which deliver 12-bit or 14-bit conversion results, respectively), the leading bits of either the 16-bit frame (serial interface) or the output pins (DB[15:12] for the ADS8528 or DB[15:14] for the ADS8548 in parallel mode) deliver a sign extension. Table 7.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com While the standby mode impacts the entire device, each device channel pair (except channel pair A, which as the master channel pair, is always active) can also be individually switched off by setting the Configuration Register bits C22, C20, and C18 (PD_x). If a certain channel pair is powered-down in this manner, the output register is disabled as shown in Figure 41.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com The auto-sleep mode is enabled by pulling pin 36 (ASLEEP) high. If the auto-sleep mode is enabled, the ADS8528/48/68 automatically reduce the current requirement to 7mA (IAVDD) after finishing a conversion; thus, the end of conversion actually activates this power-down mode.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION TYPICAL APPLICATION EXAMPLE An example of a typical application of the ADS8528/48/68 is illustrated in Figure 43. In this case, the device is used to simultaneously sample and convert the voltages and currents on three phases and the neutral line. In this example, the BUSY signal is not used by the controller while the SW generates the required signals in timely manner.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com R1 R2 AGND HVDD ADS85x8 RF CH_A0 L1 Current Signal CF OPA2211 L1 Voltage Signal AGND CF RF CH_A1 REFAP HVSS 10mF AGND R1 REFAN AGND R2 REFBN AGND 10mF HVDD CONVST_A CONVST_B CONVST_C REFBP CONVST_D RF RESET CH_B0 L2 Current Signal OPA2211 L2 Voltage Signal AGND RD CF RF Host Controller CS CF DB[15:0] CH_B1 REFIO HVSS 0.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com POWER SUPPLY The ADS8528/48/68 require four separate supplies: an analog supply for the ADC (AVDD), the buffer I/O supply for the digital interface (DVDD), and the high-voltage supplies driving the analog input circuitry (HVDD and HVSS). Generally, there are no specific requirements with regard to the power sequencing of the device.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Top View RF RF RF CF CF RF CF CF 10mF RF CF 0.
ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (August 2011) to Revision A Page • Deleted INL column from Family/Ordering Information table ............................................................................................... 2 • Changed DC Accuracy, INL parameter in ADS8568 Electical Chatacteristics table ...................
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PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2011 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8528SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 ADS8528SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS8528SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8528SPMR LQFP PM 64 1000 367.0 367.0 45.0 ADS8528SRGCR VQFN RGC 64 2000 367.0 367.0 38.0 ADS8528SRGCT VQFN RGC 64 250 210.0 185.0 35.0 ADS8548SPMR LQFP PM 64 1000 367.0 367.0 45.0 ADS8548SRGCR VQFN RGC 64 2000 367.0 367.0 38.0 ADS8548SRGCT VQFN RGC 64 250 210.0 185.0 35.
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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