Datasheet

R
2
R
1
R
F
OPA2211
HVDD
BVDD
AGND
AGND
Input #1
R
2
R
1
R
F
Input #2
HVSS
C
F
C
F
AGND
CH_A0
CH_A1 RANGE
STBY
REF /WR
EN
10 Fm
10 Fm
AGND
REFC_A
REFC_B
CONVST_B
CONVST_C
RESET
CS
RD
DB[15:0]
CONVST_A
0.47 Fm
10 Fm
AGND
REFIO
REFC_C
R
2
R
1
R
F
OPA2211
HVDD
AGND
AGND
Input #3
R
2
R
1
R
F
Input #4
HVSS
C
F
C
F
AGND
CH_B0
CH_B1
R
2
R
1
R
F
OPA2211
HVDD
AGND
AGND
Input #5
R
2
R
1
R
F
Input #6
HVSS
C
F
C
F
AGND
CH_C0
PAR/SER
CH_C1
HW/SW
WORD/BYTE
BGND
Host
Controller
ADS8556
AVDD
AVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
BVDD
BGND
HVSS
AGND
AGND
HVDD
AVDD
AVDD
AVDD
BGND
AVDD
AVDD
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
10 Fm
10 Fm
0.1 Fm
0.1 Fm
AGND
1 Fm
10 Fm
AGND
BVDD
HVSS
HVSS
ADS8556
ADS8556
ADS8557
ADS8558
www.ti.com SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
APPLICATION INFORMATION
The actual values of the resistors and capacitors
The minimum configuration of the ADS8556/7/8 in depend on the bandwidth and performance
parallel mode is shown in Figure 44. In this case, the requirements of the application. For highest data rate,
BUSY signal is not used while the SW generates the it is recommended to use a filter capacitor value of
required signals in a timely manner. TI’s OPA2211 is 1nF and a series resistor of 22Ω to fulfill the settling
used as an input driver, supporting bandwidth that requirements to an accuracy level of 16 bits within the
allows running the device at the maximum data rate. acquisition time of 280ns.
Figure 44. Minimum Configuration in Parallel Interface Mode
Copyright © 2006–2012, Texas Instruments Incorporated 35