Datasheet

ADS8556
ADS8557
ADS8558
www.ti.com SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
Table 5. Maximum Analog Current (I
AVDD
) Demand of the ADS8556/7/8
NORMAL
OPERATION POWER-UP POWER-UP
ANALOG TO TO NORMAL TO NEXT
OPERATIONAL CURRENT ACTIVATED POWER- OPERATION CONVERSION
MODE (I
AVDD
) ENABLED BY BY DOWN DELAY RESUMED BY DELAY START TIME DISABLED BY
12mA/channel
Normal operation pair (maximum Power on CONVST_x — — — — Power off
data rate)
Partial CONVST_x
2mA (channel At falling edge
power-down of Power on low while RESET pulse Immediate 6 × t
CCLK
Power off
pair x) of BUSY
channel pair x BUSY is high
A-NAP = 1 (CR Each end of At falling edge A-NAP = 0 (CR
Auto-NAP 6mA CONVST_x Immediate 6 × t
CCLK
bit) conversion of BUSY bit)
Immediate after
Power-down of 16μA (channel PD_x = 1 (CR PD_x = 0 (CR
HW/SW = 1 Immediate completing 10ms HW/SW = 0
channel pair x pair x) bit) bit)
register update
Stand-by 50μA Power on STBY = 0 Immediate STBY = 1 Immediate 10ms Power off
The AVDD supply provides power to the internal
circuitry of the ADC. It can be set in the range of 4.5V
GROUNDING
to 5.5V. Because the supply current of the device is
All GND pins should be connected to a clean ground
typically 30mA, it is not possible to use a passive
reference. This connection should be kept as short as
filter between the digital board supply of the
possible to minimize the inductance of this path. It is
application and the AVDD pin. A linear regulator is
recommended to use vias connecting the pads
recommended to generate the analog supply voltage.
directly to the ground plane. In designs without
Each AVDD pin should be decoupled to AGND with a
ground planes, the ground trace should be kept as
100nF capacitor. In addition, a single 10μF capacitor
wide as possible. Avoid connections that are too
should be placed close to the device but without
close to the grounding point of a microcontroller or
compromising the placement of the smaller capacitor.
digital signal processor.
Optionally, each supply pin can be decoupled using a
1μF ceramic capacitor without the requirement for a
Depending on the circuit density on the board,
10μF capacitor.
placement of the analog and digital components, and
the related current loops, a single solid ground plane
The BVDD supply is only used to drive the digital I/O
for the entire printed circuit board (PCB) or a
buffers and can be set in the range of 2.7V to 5.5V.
dedicated analog ground area may be used. In case
This range allows the device to interface with most
of a separated analog ground area, ensure a
state-of-the-art processors and controllers. To limit
low-impedance connection between the analog and
the noise energy from the external digital circuitry to
digital ground of the ADC by placing a bridge
the device, BVDD should be filtered. A 10Ω resistor
underneath (or next) to the ADC. Otherwise, even
can be placed between the external digital circuitry
short undershoots on the digital interface lower
and the device, because the current drawn is typically
than –300mV lead to the conduction of ESD diodes
below 2mA (depending on the external loads). A
causing current flow through the substrate and
bypass ceramic capacitor of 1μF (or alternatively, a
degrading the analog performance.
pair of 100nF and 10μF capacitors) should be placed
between the BVDD pin and pin 8.
During PCB layout, care should be taken to avoid any
return currents crossing sensitive analog areas or
The high-voltage supplies (HVSS and HVDD) are
signals.
connected to the analog inputs. Noise and glitches on
these supplies directly couple into the input signals.
SUPPLY
Place a 100nF ceramic decoupling capacitor, located
as close to the device as possible, between each of
The ADS8556/7/8 require four separate supplies: the
pins 30, 31, and AGND. An additional 10μF capacitor
analog supply for the ADC (AVDD), the buffer I/O
is used that should be placed close to the device but
supply for the digital interface (BVDD), and the
without compromising the placement of the smaller
high-voltage supplies driving the analog input circuitry
capacitor.
(HVDD and HVSS). Generally, there are no specific
requirements with regard to the power sequencing of
Figure 43 shows a layout recommendation for the
the device. However, when HVDD is supplied before
ADS8556/7/8 along with the proper decoupling and
AVDD, the internal ESD structure conducts,
reference capacitor placement and connections.
increasing IHVDD beyond the specified value.
Copyright © 2006–2012, Texas Instruments Incorporated 33