Datasheet

BUSY
ADCCH_Bx
CONVST_A/C
ACQ
CONV
Power-Down
ACQ
CONV
ACQ
ACQ
CONV
ACQ
CONV
ACQ
ADCCH_Ax/Cx
RESET
6 t´
CCLK
Min
CONVST_B
ADS8556
ADS8557
ADS8558
SBAS404B –OCTOBER 2006– REVISED JANUARY 2012 www.ti.com
The entire device, except the digital interface, can be results). The next rising edge of the CONVST_x
powered down by pulling the STBY pin low (pin 24). signal should be issued at least six conversion cycle
As the digital interface section remains active, data periods after the reset pulse and starts a new
can be retrieved while in stand-by mode. To power conversion, as shown in Figure 42. The internal
the part on again, the STBY pin must be brought reference remains active during the partial
high. The device is ready to start a new conversion power-down mode.
after 10ms required to activate and settle the internal
The auto-NAP power-down mode is enabled by
circuitry. This user-controlled approach can be used
asserting the A-NAP bit (C22) in the control register.
in applications that require lower data throughput
If the auto-NAP mode is enabled, the ADS8556/7/8
rates and lowest power dissipation. The content of
automatically reduce the current requirement to 6mA
CR is not changed during standby mode. It is not
after finishing a conversion; thus, the end of
required to perform a pin-controlled reset after
conversion actually activates the power-down mode.
returning to normal operation.
Triggering a new conversion by applying a positive
While the standby mode impacts the entire device, CONVST_x edge puts the device back into normal
each device channel pair can also be individually operation, starts the acquisition of the analog input,
switched off by setting control register bits C[15:13] and automatically starts a new conversion six
(PD_x). When reactivated, the relevant channel pair conversion clock cycles later. Therefore, a complete
requires 10ms to fully settle before starting a new conversion cycle takes 24.5 conversion clock cycles;
conversion. The internal reference remains active, thus, the maximum throughput rate in auto-NAP
except all channels are powered down at the same power-down mode is reduced to a maximum of
time. 380kSPS for the ADS8556, 395kSPS for the
ADS8557, and 420kSPS for the ADS8558 in serial
In partial power-down mode, each of the three
mode. In parallel mode, the maximum data rates are
channel pairs of the ADS8556/7/8 can be individually
500kSPS for the ADS8556, 530kSPS for the
put into a power-saving condition that reduces the
ADS8557, and 580kSPS for the ADS8558. The
current requirement to 2mA per channel pair by
internal reference remains active during the auto-NAP
bringing the corresponding CONVST_x signal low
mode. Table 5 compares the analog current
during an ongoing conversion when BUSY is high.
requirements of the devices in the different modes.
The relevant channel pair is activated again by
issuing a RESET pulse (to avoid loss of data from the
active channels, this RESET pulse should be
generated after retrieving the latest conversion
Figure 42. Partial Power-Down
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