Datasheet

CONVST
BUSY
(C20 = C21 = 0)
FS
SDO_x #3
Don’t Care
16-Bit Data CHx0
ADS8556 #3
ADS8556
#1
CONVST_A
FS
SCLK
SDO_A
SDO_B
SDO_C
ADS8556
#2
SDO_A
SDO_B
SDO_C
ADS8556
#3
SDO_A
SDO_B
SDO_C
DCIN_A
DCIN_B
DCIN_C
DC = 0
EN
CONVST_A
FS
SCLK
CONVST_A
FS
SCLK
CONVST
FS
SCLK
16-Bit Data CHx1
ADS8556 #3
16-Bit Data CHx0
ADS8556 #2
16-Bit Data CHx1
ADS8556 #2
16-Bit Data CHx0
ADS8556 #1
16-Bit Data CHx1
ADS8556 #1
DCIN_A
DCIN_B
DCIN_C
To
Processing
Unit
DC = 1
EN
DC = 1
EN
UndefinedZone
0.400
0.125
AVDD(V)
t(s)
5.500
5.000
4.000
3.000
2.000
1.000
0
1.500
SpecifiedSupply
VoltageRange
POR
TriggerLevel
0.350
4.500
ADS8556
ADS8557
ADS8558
www.ti.com SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
Figure 40. Example of Daisy-Chaining Three ADS8556s
Reset and Power-Down Modes
The device supports two reset mechanisms: a
power-on reset (POR) and a pin-controlled reset
(RESET) that can be issued using pin 28. Both the
POR and RESET act as a master reset that causes
any ongoing conversion to be interrupted, the control
register content to be set to the default value, and all
channels to be switched into sample mode.
When the device is powered up, the POR sets the
device in default mode when AVDD reaches 1.5V.
When the device is powered down, the POR circuit
requires AVDD to remain below 125mV at least
350ms to ensure proper discharging of internal
capacitors and to ensure correct behavior of the
device when powered up again. If the AVDD drops
below 400mV but remains above 125mV (see the
undefined zone in Figure 41), the internal POR
capacitor does not discharge fully and the device
requires a pin-controlled reset to perform correctly
Figure 41. POR: Relevant Voltage Levels
after the recovery of AVDD.
Copyright © 2006–2012, Texas Instruments Incorporated 31