Datasheet

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CONV TS _A

CONV TS _B

CONV TS _C

BUSY

(C20=0)

CCLK

EOC

(1)

CHAx

EOC

(1)

CHBx

EOC

(1)

CHCx

D[15:0]

XCLK

ADS8556

ADS8557

ADS8558

SBAS404B –OCTOBER 2006– REVISED JANUARY 2012

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Daisy-Chain Mode (in Serial Mode Only)

The serial interface of the ADS8556/7/8 supports a

daisy-chain feature that allows cascading of multiple

devices to minimize the board space requirements

and simplify routing of the data and control lines. In

this case, pins DB5/DCIN_A, DB4/DCIN_B, and

DB3/DCIN_C are used as serial data inputs for

channels A, B, and C, respectively. Figure 40 shows

an example of a daisy-chain connection of three

devices sharing a common CONVST line to allow

simultaneous sampling of 18 analog channels along

with the corresponding timing diagram. To activate

the daisy-chain mode, the DC

pin must be pulled

high. As a result of the time specifications t

, t

, and

, the maximum SCLK frequency that may be used

in daisy-chain mode is 27.78MHz (assuming 50%

duty cycle).

Sequential Mode (in Software Mode with External

(1) EOC = end of conversion (internal signal).

Conversion clock Only)

Figure 39. Sequential Mode Timing

The three channel pairs of the ADS8556/7/8 can be

run in sequential mode, with the corresponding

CONVST_x signals interleaved, when an external

Output Data Format

clock is used. To activate the device in sequential

The data output format of the ADS8556/7/8 is binary

mode, CR bits C11 (CLKSEL) and C23 (SEQ) must

twos complement, as shown in Table 4.

be asserted. In this case, the BUSY output indicates

a finished conversion by going low (when C20 = 0) or

For the ADS8557, which delivers 14-bit conversion

high (when C20 = 1) for only a single conversion

results, the leading two bits of the 16-bit frame are '0'

clock cycle in case of ongoing conversions of any

in the serial interface mode. In parallel interface

other channel pairs. Figure 39 shows the behavior of

mode, the output pins DB[15:14] are held low.

the BUSY output in this mode. Each conversion start

Respectively, as the ADS8558 outputs 12 bits of

should be initiated during the high phase of the

data, the first four bits of a serial 16-bit frame are

external clock, as shown in Figure 39. The minimum

zeros, in parallel interface mode the output pins

time required between two CONVST_x pulses is the

DB[15:12] are held low.

time required to read the conversion result of a

channel (pair).

Table 4. Output Data Format

BINARY CODE (HEXADECIMAL CODE)

DESCRIPTION INPUT VOLTAGE VALUE ADS8556 ADS8557 ADS8558

0111 1111 1111 1111 0001 1111 1111 1111 0000 0111 1111 1111

Positive full-scale +4V

REF

or +2V

REF

(7FFF) (1FFF) (7FF)

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

Midscale + 0.5LSB V

REF

/(2 × resolution)

(0000) (0000) (0000)

1111 1111 1111 1111 0011 1111 1111 1111 0000 1111 1111 1111

Midscale – 0.5LSB –V

REF

/(2 × resolution)

(FFFF) (3FFF) (FFF)

1000 0000 0000 0000 0010 0000 0000 0000 0000 1000 0000 0000

Negative full-scale –4V

REF

or –2V

REF

(8000) (2000) (800)