Datasheet

CONVST_A
CONVST_B
CONVST_C
BUSY
(C20=C21=0)
FS
SDO_A
CHA0
CHB0
CHA1
CHB1
CHC0
CHC1
CHA0 CHA1 CHB0 CHB1 CHC0 CHC1
FS
SDO_A
SDO_B
SEL_A =1,SEL B=_ SEL_C 0=
SEL_A =SEL_B 1,= SEL_C 0=
4 SCLK8 s
9 SCLK6 s
ADS8556
ADS8557
ADS8558
www.ti.com SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
Figure 37. Serial Interface: Data Output with One or Two Active SDOs
word and byte modes. In word mode, the first write
Hardware Mode
access updates only the upper eight bits and stores
the lower eight bits (C[23:16]) for an update that
With the HW/SW input (pin 62) set low, the device
takes place with the second write access along with
functions are controlled via the pins and, optionally,
C[15:0].
control register bits C[22:18], C[15:13], and C[9:0].
If the serial interface is used, input data containing
It is possible to generally use the part in hardware
control register contents are required with each read
mode but to switch it into software mode to initialize
access to the device in this mode (combined
or adjust the control register settings (for example,
read/write access). For initialization purposes, all 32
the internal reference DAC) and back to hardware
bits of the register should be set (bit C16 must be set
mode thereafter.
to '1' during that access to allow the update of the
entire register content). To minimize switching noise
Software Mode
on the interface, an update of the first eight bits
When the HW/SW input is set high, the device
(C[31:24]) with the remaining bits held low can be
operates in software mode with functionality set only
performed thereafter.
by the control register bits (corresponding pin settings
Figure 38 illustrates the different control register
are ignored).
update options.
If parallel interface is used, an update of all control
register settings is performed by issuing two 16-bit
Control Register (CR);
write accesses on pins DB[15:0] in word mode or four
Default Value = 0x000003FF
8-bit accesses on pins DB[15:8] in byte mode (to
The control register settings can only be changed in
avoid losing data, the entire sequence must be
software mode and are not affected when switching
finished before starting a new conversion). CS should
to hardware mode thereafter. The register values are
be held low during the two or four write accesses to
independent from input pin settings. Changes are
completely update the configuration register. It is also
active with the rising edge of WR in parallel interface
possible to update only the upper eight bits (C[31:24])
mode or with the 32nd falling SCLK edge of the
using a single write access and pins DB[15:8] in both
access in which the register content has been
updated in serial mode. Optionally, the register can
also be partially updated by writing only the upper
eight bits (C[31:24]). The CR content is defined in
Table 3.
Copyright © 2006–2012, Texas Instruments Incorporated 27