Datasheet

ADS8556
ADS8557
ADS8558
SBAS404B –OCTOBER 2006– REVISED JANUARY 2012 www.ti.com
DIGITAL significant bit (MSB), the output data are changed at
the rising edge of SCLK, so that the host processor
This section describes the digital control and the
can read it at the following falling edge. Output data
timing of the device in detail.
of the ADS8557 and ADS8558 maintain the 16-bit
format with leading zeros.
Device Configuration
Serial data input SDI are latched at the falling edge of
Depending on the desired mode of operation, the
SCLK.
ADS8556/7/8 can be configured using the external
pins and/or the control register ( CR), as shown in The serial interface can be used with one, two, or
Table 2. three output ports. These ports are enabled with pins
SEL_A, SEL_B, and SEL_C. If all three serial data
Parallel Interface output ports (SDO_A, SDO_B, and SDO_C) are
selected, the data can be read with either two 16-bit
To use the device with the parallel interface, the
data transfers or with one 32-bit data transfer. The
PAR/SER pin should be held low. The maximum
data of channels CH_x0 are available first, followed
achievable data throughput rate using the internal
by data from channels CH_x1. The maximum
clock is 630kSPS for the ADS8556, 670kSPS for the
achievable data throughput rate is 450kSPS for the
ADS8557, and 730kSPS for the ADS8558 in this
ADS8556, 470kSPS for the ADS8557, and 500kSPS
case.
for the ADS8558 in this case.
Access to the ADS8556/7/8 is controlled as illustrated
If the application allows a data transfer using two
in Figure 3 and Figure 4.
ports only, SDO_A and SDO_B outputs are used.
The device outputs data from channel CH_A0
The device can either operate with a 16-bit
followed by CH_A1 and CH_C0 on SDO_A, while
(WORD/BYTE pin set low) or an 8-bit (WORD/BYTE
data from channel CH_B0 followed by CH_B1 and
pin set high) parallel interface. If 8-bit operation is
CH_C1 occurs on SDO_B. In this case, a data
used, the HB
EN
pin selects if the low-byte (DB7 low)
transfer of three consecutive 16-bit words or one
or the high-byte (DB7 high) is available on the data
continuous 48-bit word is supported. The maximum
output DB[15:8] first.
achievable data throughput rate is 375kSPS for the
ADS8556, 390kSPS for the ADS8557, and 400kSPS
Serial Interface
for the ADS8558.
The serial interface mode is selected by setting the
The output SDO_A is selected if only one serial data
PAR/SER pin high. In this case, each data transfer
port is used in the application. The data are available
starts with the falling edge of the frame
in the following order: CH_A0, CH_A1, CH_B0,
synchronization input (FS). The conversion results
CH_B1, CH_C0, and, finally CH_C1. Data can be
are presented on the serial data output pins SDO_A,
read using six 16-bit transfers, three 32-bit transfers,
SDO_B, and SDO_C depending on the selections
or a single 96-bit transfer. The maximum achievable
made using the SEL_x pins. Starting with the most
data throughput rate is 250kSPS for the ADS8556/7
and 260kSPS for the ADS8558 in this case.
Figure 2 (the serial operation timing diagram) and
Figure 37 show all possible scenarios in more detail.
Table 2. ADS8556/7/8 Configuration Settings
HARDWARE MODE (HW/SW = 0) SOFTWARE MODE (HW/SW = 1)
CONVERSION START CONTROLLED BY SEPARATE CONVERSION START CONTROLLED BY CONVST_A
INTERFACE MODE CONVST_x PINS PIN ONLY, EXCEPT IN SEQUENTIAL MODE
Configuration using control register bits C[31:0] only;
Parallel Configuration using pins, optionally, control bits C[22:18],
status of pins 27 (only if used as RANGE input) and 63 is
(PAR/SER = 0) C[15:13], and C[9:0]
disregarded
Configuration using control register bits C[31:0] only;
status of pins 1, 27 (only if used as RANGE input), and
Serial Configuration using pins, optionally, control bits C[22:18],
63 is disregarded; each access requires a control register
(PAR/SER = 1) C[15:13], and C[9:0]; bits C[31:24] are disregarded
update via SDI (see the Serial Interface section for
details)
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