Datasheet
CONVST_A
CONVST_C
BUSY
(C20=C21=0)
CS
DB[15:0]
RD
CONVST_B
CH
A0
CH
A1
CH
C0
CH
C1
CH
A0
CH
A1
CH
C0
CONVST_B
DB[15:0]
CONVST_A
CONVST_B
CH
B0
CH
B1
CH
B0
CH
B1
CH
B0
CH
B1
CH
B0
RD
ADS8556
ADS8557
ADS8558
SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
www.ti.com
Conversion Clock
next edge of the conversion clock. CONVST_x should
remain high during the entire conversion cycle; this is
The device uses either an internally-generated or an
while the BUSY signal remains active. A falling edge
external (XCLK) conversion clock signal (in software
during an ongoing conversion puts the related ADC
mode only). In default mode, the device generates an
pair into partial power-down mode (see the Reset and
internal clock. When the CLKSEL bit is set high (bit
Power-Down Modes section for more details).
C11 in the CR), an external conversion clock of up to
20MHz (max) can be applied on pin 27. In both
For simultaneous sampling, it is recommended to
cases, 18.5 clock cycles are required for a complete
connect all associated CONVST_x pins together. If
conversion including the pre-charging of the sample
the CONVST_x signals are not tied together, a
capacitors. The external clock can remain low
maximum skew of 4 ns must be ensured for all three
between conversions.
signals in any order. A CONVST_x signal issued
during an ongoing conversion on any channel is
The conversion clock duty cycle should be 50%.
blocked, except in sequential mode (see the
However, the ADS8556/7/8 function properly with a
Sequential Mode section for more details).
duty cycle between 45% and 55%.
If a parallel interface is used, the behavior of the
CONVST_x
output port depends on which CONVST_x signals
have been issued. Figure 36 shows examples of
The analog inputs of each channel pair (CH_x0/1) are
different scenarios.
held with the rising edge of the corresponding
CONVST_x signal. Only in software mode (except
sequential mode), CONVST_A is used for all six
ADCs. The conversion automatically starts with the
NOTE: Boxed areas indicate the minimum required frame to acquire all data.
Figure 36. Data Output versus CONVST_x
24 Copyright © 2006–2012, Texas Instruments Incorporated