Datasheet

f =
-3dB
ln(2) (n+1)´
2 tp ´
ACQ
R <
SOURCE
t
ACQ
C ln(2) (n+1)´
S
- (R +R )
SER SW
ADS8556
ADS8557
ADS8558
www.ti.com SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
GENERAL DESCRIPTION
period, there is no further input current flow and the
The ADS8556/7/8 series include six 16-, 14-, and
input impedance is greater than 1MΩ. To ensure a
12-bit analog-to-digital converters (ADCs)
defined start condition, the sampling capacitors of the
respectively that operate based on the successive
ADS8556/7/8 are pre-charged to a fixed internal
approximation register (SAR) principle. The
voltage, before switching into sampling mode.
architecture is designed on the charge redistribution
principle, which inherently includes a To maintain the linearity of the converter, the inputs
sample-and-hold function. The six analog inputs are should always remain within the specified range of
grouped into three channel pairs. These channel HVSS – 0.2V to HVDD + 0.2V.
pairs can be sampled and converted simultaneously,
The minimum –3dB bandwidth of the driving
preserving the relative phase information of the
operational amplifier can be calculated using
signals of each pair. Separate conversion start
Equation 1:
signals allow simultaneous sampling on each channel
pair: on four channels or on all six channels.
These devices accept single-ended, bipolar analog
input signals in the selectable ranges of ±4V
REF
or
where:
±2V
REF
with an absolute value of up to ±12V; see the
n = 16, 14, or 12; n is the resolution of the
Analog Inputs section.
ADS8556/7/8 (1)
The devices offer an internal 2.5V/3V reference
With a minimum acquisition time of t
ACQ
= 280ns, the
source followed by a 10-bit digital-to-analog converter
required minimum bandwidth of the driving amplifier
(DAC) that allows the reference voltage V
REF
to be
is 6.7MHz for the ADS8556, 6MHz for the ADS8557,
adjusted in 2.44mV or 2.93mV steps, respectively.
or 5.2MHz for the ADS8558. The required bandwidth
The ADS8556/7/8 also offer a selectable parallel or
can be lower if the application allows a longer
serial interface that can be used in hardware or
acquisition time. A gain error occurs if a given
software mode; see the Device Configuration section
application does not fulfill the bandwidth requirement
for details.
shown in Equation 1.
A driving operational amplifier may not be required, if
ANALOG
the impedance of the signal source (R
SOURCE
) fulfills
the requirement of Equation 2:
This section addresses the analog input circuit, the
ADCs and control signals, and the reference design
of the device.
Analog Inputs
where:
n = 16, 14, or 12; n is the resolution of the ADC,
The inputs and the converters are of single-ended,
bipolar type. The absolute voltage range can be
C
S
= 10pF is the sample capacitor value for V
IN
=
selected using the RANGE pin (in hardware mode) or
±4 × V
REF
mode,
RANGE_x bits (in software mode) in the control
R
SER
= 200Ω is the input resistor value,
register ( CR) to either ±4V
REF
or ±2V
REF
. With the
and R
SW
= 130Ω is the switch resistance value
reference set to 2.5V (CR bit C18 = 0), the input
(2)
voltage range can be ±10V or ±5V. With the
reference source set to 3V (CR bit C18 = 1), an input
With t
ACQ
= 280ns, the maximum source impedance
voltage range of ±12V or ±6V can be configured. The
should be less than 2.0kΩ for the ADS8556, 2.3kΩ
logic state of the RANGE pin is latched with the
for the ADS8557, and 2.7kΩ for the ADS8558 in V
IN
falling edge of BUSY (if CR bit C20 = 0).
= ±4V
REF
mode or less than 0.8kΩ for the ADS8556,
1.0kΩ for the ADS8557, and 1.2kΩ for the ADS8558
The input current on the analog inputs depends on
in V
IN
= ±2V
REF
mode. The source impedance can be
the actual sample rate, input voltage, and signal
higher if the application allows longer acquisition time.
source impedance. Essentially, the current into the
analog inputs charges the internal capacitor array
Analog-to-Digital Converter (ADC)
only during the sampling period (t
ACQ
). The source of
the analog input voltage must be able to charge the
The devices include six ADCs that operate with either
input capacitance of 10pF in ±4V
REF
mode or 20pF in
an internal or an external conversion clock. The
±2V
REF
to a 12-, 14-, 16-bit accuracy level within the
conversion time can be as low as 1.09μs with internal
acquisition time of 280ns at maximum data rate; see
conversion clock (ADS8558). When an external clock
the Equivalent Input Circuit. During the conversion
and reference are used, the minimum conversion
time is 925ns.
Copyright © 2006–2012, Texas Instruments Incorporated 23