Datasheet

CONVST_A
CONVST_B
CONVST_C
BUSY
(C20 = C21 = 0)
CS
DB[15:0]
t
D1
t
2
t
1
RD
t
4
CH
A0
CH
A1
CH
B0
CH
B1
CH
C0
CH
C1
t
5
t
D5
t
6
t
H3
t
7
t
ACQ
t
3
t
CONV
ADS8556
ADS8557
ADS8558
www.ti.com SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
Figure 3. Parallel Read Access Timing Diagram
Parallel Interface Timing Requirements (Read Access)
(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless
otherwise noted.
ADS8556, ADS8557, ADS8558
TEST
PARAMETER CONDITION MIN TYP MAX UNIT
t
ACQ
Acquisition time 280 ns
ADS8556 1.26 µs
t
CONV
Conversion time ADS8557 1.19 µs
ADS8558 1.09 µs
t
1
CONVST_x low time 20 ns
t
2
BUSY low to CS low time 0 ns
ADS8556 40 ns
Bus access finished to next conversion
t
3
ADS8557 20 ns
start time
(2)
ADS8558 0 ns
t
4
CS low to RD low time 0 ns
t
5
RD high to CS high time 0 ns
t
6
RD pulse width 30 ns
t
7
Minimum time between two read accesses 10 ns
t
D1
CONVST_x high to BUSY high delay 5 20 ns
t
D5
RD falling edge to output data valid delay 20 ns
t
H3
Output data to RD rising edge hold time 5 ns
(1) All input signals are specified with t
R
= t
F
= 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) Refer to CS signal or RD, whichever occurs first.
Copyright © 2006–2012, Texas Instruments Incorporated 15