Datasheet

CONVST_x
BUSY
(C20 = C21 = 0)
FS
SCLK
ADS8556
SDO_x
t
D1
t
2
t
D2
t
H2
t
D4
t
1
SDI or
DCIN_x
t
S1
t
H1
Don’t Care
Don’t
Care
t
SCLK
1
32
CH_x0
MSB
t
D3
CH_x1
LSB
CH_x1
D1
CH_x1
D2
CH_x1
D3
D31 D0
D1D2
D3
t
CONV
t
ACQ
t
3
t
S3
XCLK
(C11 = 1)
t
S3
ADS8556
ADS8557
ADS8558
SBAS404B –OCTOBER 2006– REVISED JANUARY 2012 www.ti.com
TIMING CHARACTERISTICS
Figure 2. Serial Operation Timing Diagram (All Three SDOs Active)
Serial Interface Timing Requirements
(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless
otherwise noted.
ADS8556, ADS8557, ADS8558
TEST
PARAMETER CONDITION MIN TYP MAX UNIT
t
ACQ
Acquisition time 280 ns
ADS8556 1.26 µs
t
CONV
Conversion time ADS8557 1.19 µs
ADS8558 1.09 µs
t
1
CONVST_x low time 20 ns
t
2
BUSY low to FS low time 0 ns
ADS8556 40 ns
t
3
Bus access finished to next conversion start time ADS8557 20 ns
ADS8558 0 ns
t
D1
CONVST_x high to BUSY high delay 5 20 ns
t
D2
FS low to SDO_x active delay 5 12 ns
t
D3
SCLK rising edge to new data valid delay 15 ns
t
D4
FS high to SDO_x 3-state delay 10 ns
t
H1
Input data to SCLK falling edge hold time 5 ns
t
H2
Output data to SCLK rising edge hold time 5 ns
t
S1
Input data to SCLK falling edge setup time 3 ns
CONVST_x high to XCLK falling or rising edge setup
t
S3
6 ns
time
t
SCLK
Serial clock period 0.0278 10 μs
(1) All input signals are specified with t
R
= t
F
= 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
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