Datasheet

EVM Operation www.ti.com
Table 2. Factory Jumper Defaults
Jumper Function Default Condition
JP1 Controls application of the applied analog signal to A0 1-2
JP2 Controls application of the applied analog signal to A1 1-2
JP3 Controls application the CS input – Default is from J1.7 7-8
JP4 Controls the applied BVDD – default is +5VD 1-2
JP5 Controls application of the applied analog signal to C0 1-2
JP6 Controls application of the applied analog signal to B0 1-2
JP7 Controls application of the applied analog signal to B1 1-2
JP8 Controls application of the applied analog signal to C1 1-2
JP9 Controls the application the CONVST inputs – Default is from J4.17 1-2, 4-5 and 7-8
JP10 Controls the applied HVDD – default is +12VD 2-3
JP11 Controls the applied HVSS – default is –12VD 2-3
JP12 Used to connect REFIO with on-board REF5025 (U11) OPEN
4.1 Analog Inputs – J2
The analog inputs to the ADS8556EVM board can be applied to any one or all of the input channels.
Bipolar single ended inputs are to be applied between analog ground (pins 1 through 11, ODD) and input
channels A0, A1, B0, B1, C0, C1 located at J2 pins 2-12 (even) respectively. The range of the analog
input is dependent on the range setting of the ADC through SW1 position two as mentioned in section
2.2.2 of this document.
CAUTION
Carefully review the data sheet for the limitations of the analog input range, the
position of switch SW1.2, and ensure that the appropriate analog/digital
voltages are applied prior to connecting any analog input to the EVM.
4.2 Digital Controls – J1, J4 and J5
The digital controls to the EVM can be split into two primary categories – serial or parallel. By default, the
EVM is configured to operate in parallel mode under hardware control as discussed in section 2. Details of
the signals supported on the EVM are provided in the following sections.
4.2.1 Serial Control –J1
Connector J1 is used primarily for serial control. All but one of the signals on this connector are routed to
the ADS8556 through U7 and applied to the ADC when SW1.4 is in the OFF position. Details of J1 are
contained in Table 3.
Table 3. J1 – Serial Control Inputs
Pin Number Signal Description
J1.1 RESET Active HIGH RESET input. This pin is connected to digital ground through a 10K resistor R39. A high
pulse of at least 50ns will abort any ongoing conversions and reset the internal control register to
0x000003FF
J1.3 SCLK External serial clock input
J1.5
J1.7 FS/CS Active low chip select input. Routed through JP3 pins 7-8 via shunt jumper. The CS input to the
J1.9 ADS8556 has a pull up resistor R18 on the device side of JP3. CS input can be held low by placing a
shunt jumper on J1 pins 9-10 and JP3 pins 7-8 (default).
J1.11 SDI Serial data input to the ADS8556
J1.13 SDO Serial Data A output from the ADS8556. When SERBen and SERCen are disabled, serial data from all
three channel pairs is available on this pin.
8
ADS855xEVM SLAU298–November 2009
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated