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Power Supplies

2.2.5 REFen/WR (SW1.10)

Switch SW1 position 10 controls the internal reference of the ADS8556 and also directs the application of

the /WR strobe to the ADC. This switch is used in concert with both the SFT-HDW switch (SW1.3) and

SER-PAR switch (SW1.4).

2.2.5.1 Hardware Mode, Parallel Interface (EVM Default Condition)

In its default state (left – logic 1) the internal reference is enabled. When switched to the right, the internal

reference is disabled.

2.2.5.2 Software Mode, Parallel Interface

When SW1.10 is in its default state (logic 1) the function of pin 63 changes from the reference enable to

the write strobe input for the converter and the parallel data input is enabled when both /CS and /WR are

low. The reference is enabled by writing to bit 25 in the configuration register.

2.2.5.3 Hardware Mode, Serial Interface

In its default state (left – logic 1) the internal reference is enabled. When switched to the right (logic 0), the

internal reference is disabled and an external reference must be applied to REFIO.

2.2.5.4 Software Mode, Serial Interface

When operating in software mode with the serial interface, pin 63 should be tied to BGND or BVDD. The

default state of SW1.10 applies BVDD to pin 63 through pull up resistor R37. When SW1.10 is moved to

the right, BGND is applied to pin 63.

3 Power Supplies

Factory set up of the board is for a ±12V to ±15V analog front-end supply and the HV supplies on the

ADS8556, +5VA for the AVdd supply, and either +5VD or +3.3VD for the BVDD supply. All power to the

board is recommend to be sourced from a well regulated linear supply which has current limiting

capabilities. Power is to be applied through J3 (top or bottom side or the EVM).Table 1 shows the pin out

of J3.

Table 1. J3 – Power Supply Inputs

Signal Pin Number Signal

(+VA) connects to HVDD 1 2 (–VA) connects to HVSS

(+5VA) connects to AVdd, optional HVDD 3 4 (–5VA) optional HVSS

BGND 5 6 AGND

Unused 7 8 Unused

(+3.3V) optional BVDD 9 10 (+5VD) optional BVDD

For stand alone operation, power sources can be applied via various test points located on the EVM.

Refer to the schematic at the end of this document for details. The HVDD and HVSS supplies to the

ADS8556 can be selected through jumpers JP10 and JP11.

4 EVM Operation

The following section describes the default jumper locations on the ADS855xEVM along with details on

connecting the analog inputs to the board as well as the digital control signals. Details on switching the

EVM from the default parallel mode of operation to serial mode are also provided.

SLAU298–November 2009 ADS855xEVM

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