Datasheet

Digital Interface

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2.2.2 RANGE 2x – 4x (SW1.2)

The ADS8556 features two input range options. The default range for the analog input is four times the

reference voltage. When SW1.2 is switched to logic 1 (moved to the left) the range becomes two times the

reference input. Absolute input range is dependent on the reference input and the applied analog voltage.

Consult the device data sheet for specific details.

2.2.3 SFT – HDW (SW1.3)

The ADS8556 has the ability to run in hardware mode (default) or software mode. The hardware mode of

operation is the default condition for the EVM. When SW1.3 is switched to logic 1 (moved to the left)

software mode is enabled. Note the software mode requires an external conversion clock.

2.2.3.1 Software Mode – External Conversion Clock Requirements

When using software mode, the user must apply an external conversion clock to SMA connector J6.

Review the device datasheet for the external conversion clock speed/duty cycle and voltage level

requirements. Switch SW1.3 will modify the function of pin 27 on the ADS8556 and route the clock applied

to J6 through U10 to the ADC.

2.2.4 SER – PAR (SW1.4)

The ADS8556 also has the ability to communicate with the host controller through either a serial or a

parallel interface. Switch position SW1.4 facilitates this feature of the device. When SW1.4 is in its default

position (logic 0, pushed to the right) the parallel interface is selected. The 16-bit data bus is routed

through a 2:1, 16-bit bus switch (U7 – an SN74CBT16233). In parallel mode, the user can implement the

SFT – HDW switch, the RANGE switch, the BYTE switch and the REFen switch.

In serial mode (SW1.4 switched to the left), the serial clock, serial data input and serial data output are

routed to connector J1 pins 3/5, 11 and 13 respectively. J1 pins 7and 9 are routed to the chip select input

via jumper JP3.

Switch positions SW1.1 through SW1.3 have been described in the previous sections of this users guide.

Switch position SW1.10 controls the internal reference; details on this switch are described below and in

section 2.2.5 of this manual. Switch positions SW1.5–SW1.9 are described in the following sections.

2.2.4.1 Serial Interface – REFBUF ENA (SW1.5)

Switch SW1 position 5 controls the reference buffers. In hardware mode, when the switch is in its default

state (logic 0) all reference buffers are enabled and the internal reference must be applied. When switched

to the left, all reference buffers are disabled. In software mode, the internal reference buffers are

controlled through bit 24 in the control register.

2.2.4.2 Serial Interface – Daisy Chain ENA (SW1.6)

Switch SW1 position 6 controls daisy chain mode. With the switch in its default state, DCIN[A..C] are

connected to ground. When moved to the left (apply logic 1), pins 12–14 of the device under test are

connected to test points 17, 15 and 4 respectively. These pins may be wired to another ADS855xEVM and

serve as daisy chain inputs for channel pairs A, B and C.

2.2.4.3 Serial Interface – SERA/B/C Enable (SW1.7/8/9)

Switch SW1 positions 7–9 control the serial output of the ADS8556. When in the default states (logic 0),

the respective serial output is disabled. When moved to the left, the respective serial output pin becomes

active. Note the serial outputs B and C are routed to test points 12 and 13 only. Serial output A is routed

to test point 5 and connector J1.13. When using the EVM in conjunction with a modular motherboard or

interface card, the serial stream from the ADS855xEVM would be accessed through this connector.

ADS855xEVM SLAU298–November 2009

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