Datasheet

ADS8519
SLAS462D –JUNE 2007–REVISED SEPTEMBER 2010 www.ti.com
Pin Assignments
PIN
NAME NO. I/O DESCRIPTION
AGND1 2 – Analog ground. Used internally as ground reference point. Minimal current flow.
AGND2 9 – Analog ground
Busy output. Falls when a conversion is started, and remains low until the conversion is completed and
BUSY 25 O
the data are latched into the output shift register.
CS 24 – Chip select. Internally ORed with R/C.
CAP 6 Reference buffer capacitor, 2.2mF tantalum capacitor to ground.
Serial data output. Data are synchronized to DATACLK, with the format determined by the level of
SB/BTC. In the external clock mode, after 16 bits of data, the ADS8519 outputs the level input on TAG
DATA 17 O as long as CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data are valid on
both the rising and falling edges of DATACLK, and between conversions DATA stays at the level of the
TAG input when the conversion was started.
Either an input or an output, depending on the EXT/INT level. Output data are synchronized to this
DATACLK 16 I/O clock. If EXT/INT is low, DATACLK transmits 16 pulses after each conversion, and then remains low
between conversions.
DGND 14 – Digital ground
Selects external or internal clock for transmitting data. If high, data are output synchronized to the
EXT/INT 13 – clock input on DATACLK. If low, a convert command initiates the transmission of the data from the
previous conversion, along with 16 clock pulses output on DATACLK.
5, 8, 10, 11,
NC 18, 20, 22, – Not connected
23
Power down input. If high, conversions are inhibited and power consumption is significantly reduced.
PWRD 26 I
Results from the previous conversion are maintained in the output shift register.
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold
state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the data
R/C 21 I
results from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low, or a falling
edge on CS with R/C high, initiates the transmission of data from the previous conversion.
Reference input/output. Outputs internal 4.096V reference. Can also be driven by external system
REF 7 I/O
reference. In both cases, bypass to ground with a 2.2mF tantalum capacitor.
R1
IN
1 I Analog input. See Table 2 for input range connections.
R2
IN
3 I Analog input. See Table 2 for input range connections.
R3
IN
4 I Analog input. See Table 2 for input range connections.
Select straight binary or binary two's complement data output format. If high, data are output in a
SB/BTC 12 I
straight binary format. If low, data are output in a binary two's complement format.
Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high and at
SYNC 15 O least one external clock pulse has occurred when not in the read mode. See the External DATACLK
section for the external clock mode description.
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output on
TAG 19 I
DATA with a delay that depends on the external clock mode. See Figure 8 and Figure 9.
Analog supply input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1mF
V
ANA
27 I
ceramic and 10mF tantalum capacitors.
V
DIG
28 I Digital supply input. Connect directly to pin 19.
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