Datasheet
OPA627
GND
Pin1
Pin7
Pin2
Pin3
Pin4
Pin6
-15V
+15V
V
IN
2.2 Fm
100nF
2kW
22pF
2kW
22pF
2.2 Fm
2.2 Fm
100nF
2.2 Fm
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
ADS8519
OPA132
or
AGND2
GNDGND GND
GND
GND
GND
ADS8519
SLAS462D –JUNE 2007–REVISED SEPTEMBER 2010
www.ti.com
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4kΩ resistor and affects gain.
The internal buffer is capable of driving ±2mA loads, but any load can cause perturbations of the reference at the
CDAC, degrading performance. It should be pointed out that, unlike other devices with a similar input structure,
the ADS8519 does not require a second high-speed amplifier used as a buffer to isolate the CAP pin from the
signal-dependent current in the R3
IN
pin, but can tolerate it if one does exist.
The external reference voltage can vary from 3.9V to 4.2V. The reference voltage determines the size of the
least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller
reference voltages can degrade SNR.
Figure 31. Typical Driving Circuitry (±10V, No Trim)
Table 3. Control Truth Table
SPECIFIC FUNCTION CS R/C BUSY EXT/INT DATACLK PWRD SB/BTC OPERATION
Initiate conversion and 1 > 0 0 1 0 Output 0 x Initiates conversion n. Data from conversion n - 1
output data using internal clocked out on DATA synchronized to 16 clock
0 1 > 0 1 0 Output 0 x
clock pulses output on DATACLK.
1 > 0 0 1 1 Input 0 x Initiates conversion n.
0 1 > 0 1 1 Input 0 x Initiates conversion n.
Initiate conversion and
Outputs data with or without SYNC pulse. See the
output data using external 1 > 0 1 1 1 Input x x
Reading Data section.
clock
1 > 0 1 0 1 Input 0 x
Outputs data with or without SYNC pulse. See
Reading Data section.
0 0 > 1 0 1 Input 0 x
No actions 0 0 0 > 1 x x 0 x This is an acceptable condition.
Analog circuitry powered. Conversion can
x x x x x 0 x
proceed..
Power down
Analog circuitry disabled. Data from previous
x x x x x 1 x
conversion maintained in output registers.
Serial data are output in binary twos complement
x x x x x x 0
format.
Selecting output format
x x x x x x 1 Serial data are output in straight binary format.
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