Datasheet

External
DATACLK
.
2 3 4 3534 361716 20 21191
Null
D Q
A00
D Q
Null
D Q
B00
D Q
A15
D Q
A16
D Q
B15
D Q
B16
D Q
TAG(A)
TAG(B)
DATA (A)
DATA (B)
DATACLK
(both A & B)
SYNC
(both A & B)
(both A & B)
DATA ( B )
Nth Conversion Data
B15 A15B00
B13B14 B01 A00A14 A13 A01
DATA ( A )
A15 A00A13A14 A01
18
Null
A
Null
B
Null
A
ADS8519A
TAG
DATA
DATACLK
ADS8519B
TAG
DATA
DATACLK
Processor
SCLK
GPIO
GPIO
SDI
TAG(A) = 0
TAG(A) = 0
R/C
CS
R/C
CS
R/C
BUSY
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
ADS8519
www.ti.com SLAS462D –JUNE 2007–REVISED SEPTEMBER 2010
TAG FEATURE
The TAG feature allows the data from multiple ADS8519 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs, as illustrated in
Figure 28. The DATA pin of the last converter drives the processor serial data input. Data are then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
The preferred timing uses the discontinuous, external data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the t
d11
constraint (see External DATACLK section). The sampling period
must be sufficiently long to allow all data words to be read before starting a new conversion.
In Figure 28, note that a null bit separates the data word from each converter. The state of the DATA pin at the
end of a read cycle reflects the state of the TAG pin at the start of the cycle. This condition is true in all read
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode, the state of the TAG pin determines the state of the DATA pin after all 16 bits have shifted out. When
multiple converters are cascaded together, this state forms the null bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in Figure 28, the null bit becomes a zero between each data
word.
Figure 28. Timing of TAG Feature With Single Conversion (Using External DATACLK)
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Product Folder Link(s): ADS8519