Datasheet

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INTERNAL DATACLK
In the internal clock mode, data for the previous conversion are clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that it does not interfere with the
conversion process.
The DATACLK pin becomes an output when EXT/INT is low. 16 clock pulses are generated at the beginning of
each conversion after timing t
d4
is satisfied (that is, previous conversion results can only be read during the
current conversion). DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out of the
DATA pin synchronous to this clock, with each bit available on a rising and then a falling edge. The DATA pin
then returns to the state of the TAG pin input sensed at the start of transmission.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, care must be taken to
avoid corrupting the data because the external clock cannot be synchronized to the internal conversion clock.
When EXT/INT is set high, the R/C and CS signals control the read state. When the read state is initiated, the
result from the previously completed conversion is shifted out of the DATA pin synchronous to the external clock
that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum
external clock speed of 28.5MHz allows data to be shifted out quickly either at the beginning of conversion or the
beginning of sampling.
There are several modes of operation available when using an external clock. It is recommended that the
external clock run only while reading data. This mode is the discontinuous clock mode. Because the external
clock is not synchronized to the internal clock that controls conversion, slight changes in the external clock can
cause conflicts that can corrupt the conversion process. Specifications with a continuously running external clock
cannot be ensured. It is especially important that the external clock does not run during the second half of the
conversion cycle (approximately the time period specified by t
d11
; see the Timing Requirements table).
In the discontinuous clock mode, data can be read during conversion or during sampling, with or without a SYNC
pulse. Data read during a conversion must meet the t
d11
timing specification. Data read during sampling must be
complete before starting a conversion.
Whether reading during sampling or during conversion, a SYNC pulse is generated whenever at least one rising
edge of the external clock occurs while the device is not in the read state. In the Discontinuous External Clock
with SYNC mode, a SYNC pulse follows the first rising edge after the read command. Data are shifted out after
the SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse
can be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first
on the falling edge and then on the next rising edge. Thus, 17 clock pulses after the read command are required
to read on the falling edge; 18 clock pulses are necessary to read on the rising edge.
If the clock is entirely inactive when not in the read state, no SYNC pulse is generated. In this case, the first
rising clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In
this Discontinuous External Clock with No SYNC mode, 16 clocks are necessary to read the data on the falling
edge and 17 clocks for reading on the rising edge. Data always represent the conversion already completed.
Table 1 summarizes the required DATACLK pulses.
Table 1. DATACLK Pulses
DATACLK PULSES REQUIRED
DESCRIPTION WITH SYNC WITHOUT SYNC
Read on falling edge of DATACLK 17 16
Read on rising edge of DATACLK 18 17
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