Datasheet

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INL -LSBs

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DNL -LSBs

ADS8519

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SLAS462D –JUNE 2007–REVISED SEPTEMBER 2010

TYPICAL CHARACTERISTICS (continued)

INL

Figure 26.

DNL

Figure 27.

BASIC OPERATION

Two signals control conversion in the ADS8519: CS and R/C. These two signals are internally ORed together. To

start a conversion, the chip must be selected (CS low) and the conversion signal must be active (R/C low). Either

signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when

conversion starts and returns high after the data from that conversion are shifted into the internal storage

To reduce the number of control pins, CS can be tied low permanently. The R/C pin then controls conversion and

data reading exclusively. In the external clock mode, this configuration means that the ADS8519 clocks out data

whenever R/C is brought high and the external clock is active. In the internal clock mode, data are clocked out

every convert cycle, regardless of the states of CS and R/C. The ADS8519 provides a TAG input for cascading

multiple converters together.

READING DATA

The conversion result is available as soon as BUSY returns to high; therefore, data always represent the

conversion previously completed, even when it is read during a conversion. The ADS8519 outputs serial data in

either straight binary or binary two’s complement format. The SB/BTC pin controls the format. data are shifted

out MSB first. The first conversion immediately following a power-up does not produce a valid conversion result.

Data can be clocked out with either the internally-generated clock or with an external clock. The EXT/INT pin

controls this function. If an external clock is used, the TAG input can be used to daisy-chain multiple ADS8519

data pins together.

Product Folder Link(s): ADS8519