Datasheet

ADS8517
SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
PIN ASSIGNMENTS (continued)
Data clock. Either an input or an output, depending on the EXT/ INT level. Output data are
DATACLK 18 I/O synchronized to this clock. If EXT/ INT is low, DATACLK transmits 16 pulses after each
conversion, and then remains low between conversions.
Serial data output. Data are synchronized to DATACLK, with the format determined by the level
of SB/ BTC. In the external clock mode, after 16 bits of data, the ADC outputs the level input on
SDATA 19 O TAG as long as CS is low and R/ C is high. If EXT/ INT is low, data are valid on both the rising
and falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG
input when the conversion was started.
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
TAG 20 I
on DATA with a delay that depends on the external clock mode.
Byte select. Selects the eight most significant bits (low) or eight least significant bits (high) on
BYTE 21 I
parallel output pins.
Read/convert input. With CS low, a falling edge on R/ C puts the internal sample-and-hold circuit
R/ C 22 I into the hold state and starts a conversion. With EXT/ INT is low, the transmission of the data
results from the previous conversion is initiated.
Chip select. Internally ORed with R/ C. If R/ C is low, a falling edge on CS initiates a new
CS 23 I conversion. If EXT/ INT is low, this same falling edge will start the transmission of serial data
results from the previous conversion.
Busy output. At the start of a conversion, BUSY goes low and stays low until the conversion is
BUSY 24 O
completed and the digital outputs have been updated.
Power-down input. If high, conversions are inhibited and power consumption is significantly
PWRD 25 I
reduced. Results from the previous conversion are maintained in the output shift register.
Reference disable. REFD high shuts down the internal reference. The external reference is
REFD 26 I
required for conversions.
V
ANA
27 ADC core supply. Nominally +5 V. Decouple with 0.1- µ F ceramic and 10- µ F tantalum capacitors.
V
DIG
28 I/O supply. Nominally +1.8 V.
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