Datasheet

External Data Clock
ADS8517
SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
To use an external data clock, tie EXT/ INT (pin 8) high. The external data clock is not and cannot be
synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the
output mode of the ADS8517, CS (pin 23) must be low and R/ C (pin 22) must be high. DATACLK must be high
for 20% to 70% of the total data clock period; the clock rate can be between dc and 10 MHz. Serial data from
conversion N can be output on SDATA (pin 19) after conversion N completes or during conversion N+1.
An obvious way to simplify control of the converter is to tie CS low and use R/ C to initiate conversions.
While this configuration is perfectly acceptable, there is a possible problem when using an external data clock. At
an indeterminate point from 12 µ s after the start of conversion N until BUSY rises, the internal logic shifts the
results of conversion N into the output register. If CS is low, R/ C high, and the external clock is high at this point,
data are lost. Consequently, with CS low, either R/ C and/or DATACLK must be low during this period to avoid
losing valid data.
External Data Clock (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS
low and R/ C high, valid data from conversion N are output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the
external data clock. The LSB is valid on the 16th falling edge and 17th rising edge of the data clock. TAG (pin
20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 17th
falling edge and the 18th rising edge of DATACLK; the second input bit is valid on the 18th falling edge and the
19th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output
registers are updated with the results from the next conversion. Refer to Table 6 and Figure 35 for more
information.
External Data Clock (During a Conversion)
After conversion N has been initiated, valid data from conversion N – 1 can be read and are valid up to 2.2 µ s
after the start of conversion N. Do not attempt to clock out data from 2.2 µ s after the start of conversion N until
BUSY (pin 24) rises; doing so results in data loss.
NOTE:
For the best possible performance when using an external data clock, data should not
be clocked out during a conversion.
The switching noise of the asynchronous data clock can cause digital feedthrough, degrading converter
performance. Refer to Table 6 and Figure 36 for more information.
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