Datasheet

Serial Output
Internal Data Clock (During a Conversion)
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009
Parallel Output (During a Conversion)
After conversion N has been initiated, valid data from conversion N – 1 can be read and are valid up to 2.2 µ s
after the start of conversion N. Do not attempt to read data beyond 2.2 µ s after the start of conversion N until
BUSY (pin 24) goes high; doing so may result in reading invalid data. Refer to Table 5 , Figure 30 , and Figure 31
for timing constraints.
Table 5. Conversion and Data Timing with Parallel Interface at T
A
= – 40 ° C to +85 ° C
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
Convert pulse width 0.04 5 µ s
t
2
Data valid delay after R/ C low 2.3 2.5 µ s
t
3
BUSY delay from start of conversion 20 85 ns
t
4
BUSY low 2.3 2.5 µ s
t
5
BUSY delay after end of conversion 90 ns
t
6
Aperture delay 40 ns
t
7
Conversion time 1.8 2.2 µ s
t
8
Acquisition time 2.7 µ s
t
9
Bus relinquish time 10 83 ns
t
10
BUSY delay after data valid 20 60 ns
t
11
Previous data valid after start of conversion 1.8 2.2 µ s
t
21
R/ C to CS setup time 10 ns
t
7
+ t
8
Throughput time 5 µ s
Data can be clocked out with the internal data clock or an external data clock. When using the serial output, be
careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), because these pins come out of a High-Z state
whenever CS (pin 23) is low and R/ C (pin 22) is high. The serial output cannot be 3-stated and is always active.
Refer to the Applications Information section for specific serial interfaces. If an external clock is used, the TAG
input can be used to daisy-chain multiple ADS8517 data pins together.
To use the internal data clock, tie EXT/ INT (pin 8) low. The combination of R/ C (pin 22) and CS (pin 23) low
initiates conversion N and activates the internal data clock (typically, a 900-kHz clock rate). The ADS8517
outputs 16 bits of valid data, MSB first, from conversion N – 1 on SDATA (pin 19), synchronized to 16 clock pulses
output on DATACLK (pin 18). The data are valid on both the rising and falling edges of the internal data clock.
The rising edge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK remains
low until the next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the
start of transmission. Refer to Table 6 and Figure 33 for more information.
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