Datasheet

ADS8515
www.ti.com
SLAS460D JUNE 2007REVISED SEPTEMBER 2010
CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-mF capacitor should be placed as close to the
CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and
compensation for the output of the internal buffer. Using a capacitor any smaller than 1 mF can cause the output
buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 mF have
little affect on improving performance. The ESR (equivalent series resistance) of these compensation capacitors
is also critical. Keep the total ESR under 3 . See the Typical Characteristics section for how the worst case INL
is affected by ESR.
The output of the buffer is capable of driving up to 2 mA of current to a dc load, but any external load from the
CAP pin may degrade the linearity of the ADS8515. Using an external buffer allows the internal reference to be
used for larger dc loads and ac loads. Do not attempt to directly drive an ac load with the output voltage on CAP.
This causes performance degradation of the converter. The ESR (equivalent series resistance) of these
compensation capacitors is also critical. Keep the total ESR under 3 . See the Typical Characteristics section
concerning how ESR affects performance.
LAYOUT
POWER
The analog power pin (V
ANA
) and digital power pin (V
DIG
) can be tied together from the same +5V power supply,
or from two different power-supply sources. The ADS8515 uses 90% of its power from the analog circuitry, and
therefore should be considered as an analog component. Care must be taken to ensure that both the analog and
digital power supplies power on before any voltage is applied to the analog input pin. Failure to do so may create
a latch-up condition. There is no power sequencing requirement between V
ANA
and V
DIG
.
GROUNDING
Three ground pins are present on the ADS8515. DGND is the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals internal to the A/D converter are referenced. AGND1 is
more susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D converter should be tied to the analog ground plane, separated from the system
digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to
the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground
currents from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS8515, compared to
the FET switches on other CMOS A/D converters, releases 5% to 10% of the charge. There is also a resistive
front end which attenuates any charge which is released. The end result is a minimal requirement for the
antialias filter on the front end. Any op amp sufficient for the signal in an application is sufficient to drive the
ADS8515.
The resistive front end of the ADS8515 also provides an assured ±25-V overvoltage protection. In most cases,
this eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS8515 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to
isolate the A/D converter from other peripherals on the same bus. The 3-state outputs can also be used when
the A/D converter is the only peripheral on the data bus.
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8515 has an internal LSB size of
38 mV. Transients from fast switching signals on the parallel port, even when the A/D converter is 3-stated, can
be coupled through the substrate to the analog circuitry causing degradation of converter performance.
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