Datasheet
ADS8515
SLAS460D –JUNE 2007–REVISED SEPTEMBER 2010
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STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) held low for a minimum of 40 ns immediately puts the
sample/hold of the ADS8515 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low
until conversion n is completed and the internal output register has been updated.
The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 ms between convert
commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY
states and Figure 21, Figure 22, and Figure 23 for the timing diagrams.
CS and R/C are internally ORed and level triggered. There is no requirement regarding which input goes low first
when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less
critical input is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The
parallel output becomes active whenever R/C goes high. Refer to the Reading Data section.
Table 1. Control Line Functions for Read and Convert
CS R/C BUSY OPERATION
1 X X None. Databus is in Hi-Z state.
↓ 0 1 Initiates conversion n. Databus remains in Hi-Z state.
0 ↓ 1 Initiates conversion n. Databus enters Hi-Z state.
0 1 ↑ Conversion n completed. Valid data from conversion n on the databus.
↓ 1 1 Enables databus with valid data from conversion n.
↓ 1 0 Enables databus with valid data from conversion –1
(1)
. Conversion n in progress.
0 ↑ 0 Enables databus with valid data from conversion –1
(1)
. Conversion n in progress.
0 0 ↑ New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C
must be high when BUSY goes high.
X X 0 Conversion n in progress.
(1) See Figure 21 and Figure 22 for constraints on data valid from conversion n – 1.
READING DATA
The ADS8515 outputs full or byte-reading parallel data in binary twos complement data output format. The
parallel output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C
3-states the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on
pins 6 to 13 and pins 15 to 22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle.
Refer to Table 2 for ideal output codes and Figure 20 for bit locations relative to the state of BYTE.
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT BINARY TWOS COMPLEMENT
DESCRIPTION ANALOG INPUT
BINARY CODE HEX CODE
Full-scale range ±10 V
Least significant bit (LSB) 305 mV
Full scale (10 V – 1 LSB) 9.999695 V 0111 1111 1111 1111 7FFF
Midscale 0 V 0000 0000 0000 0000 0000
One LSB below midscale –305 mV 1111 1111 1111 1111 FFFF
–Full scale –10 V 1000 0000 0000 0000 8000
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