Datasheet

BUSY
SDATA
DATACLK
CS
EXT/INT
PCS0/SS
MOSI
SCK
QSPI ADS8513
Convert Pulse
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data Valid on Falling Edge)
QSPI Port is in Slave Mode
The ADC is the SPI master.
CONV
DATA
DATACLK
CS
BYTE
PCS0
PCS1
SCK
QSPI ADS8513
CPOL = 0
CPHA = 0
+ 5 V
EXT/INT
MISO
CONV
ADS8513
SLAS486C – JUNE 2007 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
Figure 50. QSPI Interface to the ADS8513
Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line. When
a transition from high to low occurs on slave select ( SS) from BUSY (indicating the end of the current
conversion), the port can be enabled. If this enabling is not done, the microcontroller and the A/D converter may
be out-of-sync.
Figure 51 shows another interface between the ADS8513 and a QSPI-equipped microcontroller that allows the
microcontroller to give the convert pulses while also allowing multiple peripherals to be connected to the serial
bus. This interface and the following discussion assume a master clock for the QSPI interface of 16.78MHz.
Notice that the serial data input of the microcontroller is tied to the MSB (D7) of the ADS8513 instead of the
serial output (SDATA). Using D7 instead of the serial port offers 3-state capability that allows other peripherals to
be connected to the MISO pin. When communication is desired with those peripherals, PCS0 and PCS1 should
be left high, which keeps D7 3-stated.
Figure 51. QSPI Interface to the ADS8513, Processor Initiates Conversions
In this configuration, the QSPI interface is actually set to do two different serial transfers. The first, an 8-bit
transfer, causes PCS0 ( CONV) and PCS1 ( CS) to go low, starting a conversion. The second, a 16-bit transfer,
causes only PCS1 ( CS) to go low. This point is when the valid data are transferred.
For both transfers, the DT register (delay after transfer) is used to cause a 19 µ s delay. The interface is also set
up to wrap to the beginning of the queue. In this manner, the QSPI is a state machine that generates the
appropriate timing for the ADS8513. This timing is thus locked to the crystal-based timing of the microcontroller
and not interrupt-driven. So, this interface is appropriate for both ac and dc measurements.
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