Datasheet

1
t
Converter
Full-Scale
InputVoltage
Range
0000
ConversionClock
IncorrectResult
CorrectResult
ActualInput
Voltage
InternalDAC
Voltage
WrongBitDecisionMadeHere
ProperSAROperation
SAROperationafter
WrongBitDecision
1
(1 1)0110
ExternalNoise
ConversionStart
(HoldMode)
ADS8513
SLAS486C – JUNE 2007 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
If the result so far is getting very close to the actual input voltage, then the comparison involves two voltages that
are very close together. The ADS8513 has been designed so that the internal noise sources are at a minimum
just before the comparator result is latched. However, if an external digital signal transitions at this time, a great
deal of noise will be coupled into the sensitive analog section of the ADS8513. Even if this noise produces a
difference between the two voltages of only 2mV, the conversion result will be off by 52 counts or least significant
bits (LSBs). (The internal LSB size of the ADS8513 is 38 µ V, regardless of the input range.)
Once a digital transition has caused the comparator to make a wrong bit decision, the decision cannot be
corrected (unless some type of error correction is employed). All subsequent bit decisions will then be wrong.
Figure 48 shows a successive approximation process that has gone wrong. The dashed line represents what the
correct bit decisions should have been. The solid line represents the actual result of the conversion.
Figure 48. SAR Operation When External Noise Affects the Conversion
Keep in mind that the time period when the comparator is most sensitive to noise is fairly small. Also, the peak
portion of the noise event produced by a digital transition is fairly brief, because most digital signals transition in a
few nanoseconds. The subsequent noise may last for a period of time longer than this and may induce further
effects that require a longer settling time. However, in general, the event is over within a few tens of
nanoseconds.
For the ADS8513, error correction is done when the tenth bit is decided. During this bit decision, it is possible to
correct limited errors that may have occurred during previous bit decisions. However, after the tenth bit, no such
correction is possible. Note that for the timing diagrams shown in Figure 36 , Figure 39 , Figure 40 , Figure 41 , and
Figure 42 , all external digital signals should remain static from 8 µ s after the start of a conversion until BUSY
rises. The tenth bit is decided approximately 10 µ s to 11 µ s into the conversion.
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