Datasheet

LAYOUT
POWER FOR TSSOP-20 PACKAGE
GROUNDING
SIGNAL CONDITIONING
SENSITIVITY TO EXTERNAL DIGITAL SIGNALS
ADS8513
www.ti.com ...................................................................................................................................................... SLAS486C – JUNE 2007 – REVISED JANUARY 2009
For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the
analog and digital grounds together. As noted in the Electrical Characteristics table, the ADS8513 uses 90% of
its power for the analog circuitry. The ADS8513 should be considered as an analog component.
The +5V power for the A/D converter should be separate from the +5V used for the system digital logic.
Connecting +V
BD
directly to a digital supply can reduce converter performance because of switching noise from
the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for
the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be
used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly
filter the supply. Either using a filtered digital supply or a regulated analog supply, both +V
BD
and +V
A
should be
tied to the same +5V source.
All of the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system
digital logic ground to achieve optimum performance. Both analog and digital ground planes should be tied to the
system ground as close to the power supplies as possible. This layout helps to prevent dynamic digital ground
currents from modulating the analog ground through a common impedance to power ground.
The FET switches used for the sample-and-hold on many CMOS A/D converters release a significant amount of
charge injection that can cause the driving op amp to oscillate. The amount of charge injection that results from
the sampling FET switch on the ADS8513 is approximately 5% to 10% of the amount on similar A/D converters
with the charge redistribution digital-to-analog converter (DAC) CDAC architecture. There is also a resistive
front-end that attenuates any charge which is released. The end result is a minimal requirement for the drive
capability on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an
application is sufficient to drive the ADS8513.
The resistive front-end of the ADS8513 also provides a specified ± 25V overvoltage protection. In most cases,
this architecture eliminates the need for external over-voltage protection circuitry.
All successive approximation register-based A/D converters are sensitive to external noise sources. For the
ADS8513 and similar A/D converters, this noise most often originates because of the transition of external digital
signals. While digital signals that run near the converter can be the source of the noise, the biggest problem
occurs with the digital inputs to the converter itself.
In many cases, the system designer may not be aware that there is a problem or the potential for a problem. For
a 12-bit system, these problems typically occur at the least significant bits and only at certain places in the
converter transfer function. For a 16-bit converter, the problem can be much easier to spot.
For example, the timing diagram in Figure 36 shows that the CONV signal should return high sometime during
time t
2
. In fact, the CONV signal can return high at any time during the conversion. However, after time t
2
, the
transition of the CONV signal has the potential of creating a good deal of noise on the ADS8513 die. If this
transition occurs at just precisely the wrong time, the conversion results could be affected. In a similar manner,
transitions on the DATACLK input could affect the conversion result.
For the ADS8513, there are 16 separate bit decisions that are made during the conversion. The most significant
bit decision is made first, proceeding to the least significant bit at the end of the conversion. Each bit decision
involves the assumption that the bit being tested should be set. This action is combined with the result that has
been achieved so far. The converter compares this combined result with the actual input voltage. If the combined
result is too high, the bit is cleared. If the result is equal to or lower than the actual input voltage, the bit remains
high. This effect is why the basic architecture is referred to as a successive approximation register (SAR).
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