Datasheet

BUSY
CONV
t
24
t
4
t
5
DATACLK
t
25
1 2 n n+1 15 16
DATA
MSB
Bit14
Bitn
Bitn-1
Bit1
LSB
CHIP SELECT
ActiveHI-Z HI-Z
BUSY,DATA,
DATACLK
(1)
CS
t
27
t
26
NOTE:(1)DATACLKisanoutputonlywhenEXT/INT isLOW.
ADS8513
www.ti.com ...................................................................................................................................................... SLAS486C – JUNE 2007 – REVISED JANUARY 2009
External DATACLK Active After the Conversion and During the Next Conversion
Figure 42 shows a method that combines the two previous approaches. This method works very well for
microcontrollers that do serial transfers eight bits at a time and for slower microcontrollers. For example, if the
fastest serial clock that the microcontroller can produce is 1 µ s, the approach shown in Figure 40 would result in a
diminished throughput (26kSPS maximum conversion rate). The method described in Figure 41 could not be
used without risk of affecting the conversion result (the clock would have to be active after time t
2
). Therefore, the
approach in Figure 42 results in an improved throughput rate (33kSPS maximum with a 1 µ s clock), and
DATACLK is not active after time t
2
.
Figure 42. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the
Next Conversion (EXT/ INT High, CS Low)
The CS input allows the digital outputs of the ADS8513 to be disabled and gates the external DATACLK signal
when EXT/ INT is high. See Figure 43 for the enable and disable time associated with CS and Figure 37 for a
logic diagram of the ADS8513. The digital outputs can be disabled at any time.
Note that a conversion is initiated on the falling edge of CONV even if CS is high. If the EXT/ INT input is low
(internal DATACLK) and CS is high during the entire conversion, the previous conversion result is lost (that is,
the serial transmission occurs but DATA and DATACLK are disabled).
Figure 43. Enable and Disable Timing for Digital Outputs
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