Datasheet

BUSY
CONV
t
1
t
5
DATACLK
t
4
t
23
t
22
t
21
t
20
t
19
1 2 3 4 14 15 16
DATA
MSB Bit14 Bit13 Bit2 Bit1
LSB
3 4
BUSY
CONV
t
2
t
1
DATACLK
t
24
t
25
t
23
t
22
t
21
t
20
t
19
1
1
2 15 16
DATA
MSB Bit14 Bit13 Bit1 LSB MSB
ADS8513
SLAS486C – JUNE 2007 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
Before reading the next three paragraphs, consult the Sensitivity to External Digital Signals section of this data
sheet. This section explains many of the concerns regarding how and when to apply the external DATACLK
signal.
External DATACLK Active After the Conversion
The preferred method of obtaining the conversion result is to provide the DATACLK signal after the conversion
has been completed and before the next conversion starts, as shown in Figure 40 . Note that the DATACLK
signal should be static before the start of the next conversion. If this limit is not observed, the DATACLK signal
could affect the acquired.
Figure 40. Serial Data Timing, External Clock, Clocking After the Conversion Completes (EXT/ INT High,
CS Low)
External DATACLK Active During the Next Conversion
Another method of obtaining the conversion result is shown in Figure 41 . Because the output shift register is not
updated until the end of the conversion, the previous result remains valid during the next conversion. If a fast
clock ( ≥ 2MHz) can be provided to the ADS8513, the result can be read during time t
2
. During this time, the noise
from the DATACLK signal is less likely to affect the conversion result.
Figure 41. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/ INT High, CS
Low)
16 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8513