Datasheet

CONV
t
6
– t
25
t
25
BUSY
NOTE:Updateoftheinternalshiftregisteroccursinthe
shadedregion.IfEXT/INT isHIGH,thenDATACLK
mustbeLOWorCSmustbeHIGHduringthistime.
INTERNAL DATACLK
t
17
DATACLK
BUSY
CONV
t
1
t
12
t
18
t
16
t
14
t
13
t
15
1 12 3 14 15 16
DATA
MSB Bit14
Bit13
Bit2 Bit1 LSB
MSB
EXTERNAL DATACLK
ADS8513
www.ti.com ...................................................................................................................................................... SLAS486C – JUNE 2007 – REVISED JANUARY 2009
Figure 38. Shift Register Update Timing
With EXT/ INT tied low, the result from conversion ‘ n ’ is serially transmitted during conversion ‘ n+1 ’ , as shown in
Figure 39 and with the timing given in Table 2 . Serial transmission of data occurs only during a conversion.
When a transmission is not in progress, DATA and DATACLK are low.
Figure 39. Serial Data Timing, Internal Clock (EXT/ INT and CS Low)
During the conversion, the results of the previous conversion are transmitted via DATA, while DATACLK
provides the synchronous clock for the serial data. The data format is 16-bit, Binary Two ’ s Complement, MSB
first. Each data bit is valid on both the rising and falling edges of DATACLK. BUSY is low during the entire serial
transmission and can be used as a frame synchronization signal.
With EXT/ INT tied high, the result from conversion ‘ n ’ is clocked out after the conversion has completed, during
the next conversion ( ‘ n+1 ’ ), or a combination of these two. Figure 40 shows the case of reading the conversion
result after the conversion is complete. Figure 41 describes reading the result during the next conversion.
Figure 42 combines the important aspects of Figure 40 and Figure 41 for reading part of the result after the
conversion is complete and the balance during the next conversion.
The serial transmission of the conversion result is initiated by a rising edge on DATACLK. The data format is
16-bit, Binary Two ’ s Complement, MSB first. Each data bit is valid on the falling edge of DATACLK. In some
cases, it might be possible to use the rising edge of the DATACLK signal. However, one extra clock period (not
shown in Figure 40 , Figure 41 , and Figure 42 ) is needed for the final bit.
The external DATACLK signal must be low or CS must be high before BUSY rises (see time t
25
in Figure 41 and
Figure 42 ). If this limit is not observed during this time, the output shift register of the ADS8513 is not updated
with the conversion result. Instead, the previous contents of the shift register remain and the new result is lost.
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