Datasheet

READING DATA
QD
S0
Q
Updateoftheshift
registeroccursjustprior
to RisingBUSY
(1)
D
S1
QD
S2
QD
S14
QD
S15
Q
ShiftRegister
WorkingRegister
ConverterCore
D
SOUT
QD
W0
Q
Eachflip-flopinthe
workingregisteris
latchedasthe
conversionproceeds
D
W1
QD
W2
QD
W14
QD
W15
• • •
Delay
DATA
BUSY
DATACLK
CDAC
ControlLogic
Clock
REF
EXT/INT
CONV
CS
NOTE:(1)IfEXT/ isHIGH(externalclock),DATACLKisHIGH,and isLOWduringINT CS
thistime,theshiftregisterwillnotbeupdatedandtheconversionresultwillbelost.
ADS8513
SLAS486C – JUNE 2007 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
The ADS8513 digital output is in Binary Two ’ s Complement (BTC) format. Table 3 shows the relationship
between the digital output word and the analog input voltage under ideal conditions.
Table 3. Output Codes and Ideal Input Voltages
DESCRIPTION ANALOG INPUT RANGE DIGITAL OUTPUT
Full-scale range ± 10V 0.5V to 4.5V BINARY TWOS COMPLEMENT
Least significant bit (LSB) 305 µ V 61 µ V BINARY CODE HEX CODE
+Full-scale (FS – 1LSB) 9.999695V 4.499939V 0111 1111 1111 1111 7FFF
Midscale 0V 2.5V 0000 0000 0000 0000 0000
One LSB below midscale – 305 µ V 2.499939 µ V 1111 1111 1111 1111 FFFF
– Full-scale – 10V 0.5V 1000 0000 0000 0000 8000
Figure 37 shows the relationship between the various digital inputs, digital outputs, and internal logic of the
ADS8513. Figure 38 illustrates when the internal shift register of the ADS8513 is updated and how this update
relates to a single conversion cycle. Together, these two figures define a very important aspect of the ADS8513:
the conversion result is not available until after the conversion is complete. The implications of this
protocol are discussed in the following sections.
Figure 37. Block Diagram of the ADS8513 Digital Inputs and Outputs
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