Datasheet

BASIC OPERATION
INTERNAL DATACLK
1
2
3
4
5
6
7
8
R1
IN
GND
R2
IN
R3
IN
BUF
CAP
REF
GND
V
S
PWRD
BUSY
CS
CONV
EXT/INT
DATA
DATACLK
16
15
14
13
12
11
10
9
ADS8513
±10V
+5V
C
3
1µF
C
4
0.01µF
C
1
0.1µF
C
2
10µF
C
5
1µF
+
+
ConvertPulse
40nsmin
+
FrameSync(optional)
EXTERNAL DATACLK
1
2
3
4
5
6
7
8
R1
IN
GND
R2
IN
R3
IN
BUF
CAP
REF
GND
V
S
PWRD
BUSY
CS
CONV
EXT/INT
DATA
DATACLK
16
15
14
13
12
11
10
9
ADS8513
±10V
NOTE:(1) Tie toGNDiftheoutputswillalwaysbeactive.CS
+5V
+5V
C
1
0.1µF
C
2
10µF
C
5
1µF
+
ConvertPulse
40nsmin
+
Interrupt(optional)
ExternalClock
ChipSelect(optional
(1)
)
C
3
1µF
C
4
0.01µF
+
ADS8513
www.ti.com ...................................................................................................................................................... SLAS486C – JUNE 2007 – REVISED JANUARY 2009
Figure 34 shows a basic circuit to operate the ADS8513 with a ± 10V input range using an internal DATACLK. To
begin a conversion and serial transmission of the results from the previous conversion, a falling edge must be
provided to the CONV input. BUSY goes low to indicate that a conversion has started, and stays low until the
conversion is complete. During the conversion, the results of the previous conversion are transmitted via DATA
while DATACLK provides the synchronous clock for the serial data. The data format is 16-bit, binary twos
complement, MSB first. Each data bit is valid on both the rising and falling edge of DATACLK. BUSY is low
during the entire serial transmission and can be used as a frame synchronization signal.
Figure 34. Basic Operating Circuit, ± 10V Input Range, Internal DATACLK
Figure 35 shows another basic circuit to operate the ADS8513 with a ± 10V input rangeusing an external
DATACLK. To begin a conversion, a falling edge must be provided to the CONV input. BUSY goes low to
indicate that a conversion has started,and stays low until the conversion is complete. Just before BUSY rises
near the end of the conversion, the conversion result held in the internal working register is transferred to the
internal shift register.
The internal shift register is clocked via the DATACLK input. The recommended method of reading the
conversion result is to provide the serial clock after the conversion has completed. See External DATACLK under
the Reading Data section of this data sheet for more information.
Figure 35. Basic Operating Circuit, ± 10V Input Range, External DATACLK
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